David Palomeque-Mangut, Á. Rodríguez-Vázquez, M. Delgado-Restituto
{"title":"A Wide-Range, High-Voltage, Floating Level Shifter with Charge Refreshing in a Standard 180 nm CMOS Process","authors":"David Palomeque-Mangut, Á. Rodríguez-Vázquez, M. Delgado-Restituto","doi":"10.1109/LASCAS53948.2022.9789044","DOIUrl":null,"url":null,"abstract":"A high-voltage (HV) floating level shifter which slides digital signals by varying the low supply rail from ground to V<inf>S</inf><inf>S</inf><inf>H</inf> while preserving the input signal swing is proposed. The cell is based on a periodically-refreshed charge pump circuit and it is suitable for non-HV CMOS processes. Input signals can be non-periodic. The circuit has been designed and implemented in a standard 180 nm 1.8V/3.3V CMOS node, occupying 0.02 mm<sup>2</sup>. Post-layout simulations show that V<inf>S</inf><inf>S</inf><inf>H</inf> voltage can safely range from 0.5 V to 9.5 V. The delay response of the circuit is 1.9 ns and it consumes 13.9 μW.","PeriodicalId":356481,"journal":{"name":"2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/LASCAS53948.2022.9789044","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
A high-voltage (HV) floating level shifter which slides digital signals by varying the low supply rail from ground to VSSH while preserving the input signal swing is proposed. The cell is based on a periodically-refreshed charge pump circuit and it is suitable for non-HV CMOS processes. Input signals can be non-periodic. The circuit has been designed and implemented in a standard 180 nm 1.8V/3.3V CMOS node, occupying 0.02 mm2. Post-layout simulations show that VSSH voltage can safely range from 0.5 V to 9.5 V. The delay response of the circuit is 1.9 ns and it consumes 13.9 μW.
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