Design of Asynchronous Pipelines with QDI Template Using Commercial FPGA

The asynchronous paradigm has interesting features due to the lack of the clock signal and is another option for project of digital systems. This paradigm has several design styles, where the asynchronous pipeline style is interesting due to its high performance and the simplicity of its control. There are two classes of an asynchronous pipeline: Bundled-data and Quasi Delay Insensitive (QDI). The QDI circuit class is notable for its robustness and high modularity. In this paper, we propose two new asynchronous architectures in the pipeline style for QDI circuits. Unlike many QDI proposals, these architectures focus on platforms FPGA (Field Programmable Gate Array) and VLSI (Very Large-Scale Integration) standard cell. The two new architectures were prototyped in FPGAs devices, applied in a set of benchmarks, and compared with the literature's QDI pipeline architecture, which is also focused on FPGA. From the results obtained by the three architectures, we highlight the increase in throughput of 51.2% of the proposed architecture compared to the literature's architecture.