Fault-Tolerant Finite State Machine Quasi Delay Insensitive in Commercial FPGA Devices

Abstract

Because electronic devices cannot avoid soft errors (unexpected and non-destructive signal transitions) occurred in radiation environment, circuit redundancy approaches are adopted for such situations, which lead to huge penalties in area and power dissipation resources in digital design. QDI-AFSM (Quasi-Delay Insensitive-Asynchronous Finite State Machine), which uses dual-rail variables, may be an interesting solution for fault-tolerant digital systems if some additional circuitry is used for soft errors detection. In FPGA, this issue is particularly concerning because, in such target devices, any digital circuitry is modeled using programmable LUTs (Look Up Tables) where a flipped bit cannot be recovered unless a new programming procedure be done. The proposed architecture for finite state machines in FPGA devices enhances robustness to a QDI digital design inserting a novel output register based on sequential logic gates that validate each dual-rail output variable on the system according to the current processing cycle and output state. The reduced average penalties in area, power, and latency for the proposed fault-tolerant architecture may be advantageous compared to TMR approaches.