Low Power Frequency Dividers using TSPC logic in 28nm FDSOI Technology

In this work, Integer N frequency dividers are designed in a dual loop PLL circuit which is applicable at reference frequency 40.92MHz and 400MHz and for a feedback input frequency 0.8GHz-6.3GHz with very low power consumption and small die area. A fast and energy-efficient True Single Phase Clock (TSPC) D-Flip Flops with a controlled pre-charger circuit has been explained for designing reference and feedback frequency dividers (sequentially 4-bit De-Counter and 8-bit De-Counter). The phase noise (PN) of the dividers always remains at −130dBc/Hz at 1MHz offset. The circuit was designed and implemented in 28nm FDSOI technology and the divider's maximum current consumption is $208\mu \mathrm{A}$ at 1 V.