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2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)最新文献

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Impact of Thread Parallelism on the Soft Error Reliability of Convolution Neural Networks 线程并行性对卷积神经网络软误差可靠性的影响
2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS) Pub Date : 2022-03-01 DOI: 10.1109/LASCAS53948.2022.9789088
Geancarlo Abich, Rafael Garibotti, Jonas Gava, R. Reis, Luciano Ost
{"title":"Impact of Thread Parallelism on the Soft Error Reliability of Convolution Neural Networks","authors":"Geancarlo Abich, Rafael Garibotti, Jonas Gava, R. Reis, Luciano Ost","doi":"10.1109/LASCAS53948.2022.9789088","DOIUrl":"https://doi.org/10.1109/LASCAS53948.2022.9789088","url":null,"abstract":"Convolution neural networks (CNNs) have been incorporated into resource-constrained edge devices to intelligently manage and process local data coming from a variety of sensors. Thread parallelism has been used to boost the performance of neural networks, but only few works address the effect of these parallel modifications on the soft error reliability of underlying models running on edge devices. In this sense, this work aims to assess the soft error reliability of a multi-threaded version of a CNN model developed based on the Arm CMSIS-NN kernels. Results show that the developed threaded CNN model increases performance at the cost of low memory footprint overhead. Promoted multi-threaded CNN model also provides better soft error reliability w.r.t. the original sequential version.","PeriodicalId":356481,"journal":{"name":"2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127156961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Hybrid Comparator and Window Switching Scheme for low-power SAR ADC 低功耗SAR ADC的混合比较器和窗口开关方案
2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS) Pub Date : 2022-03-01 DOI: 10.1109/LASCAS53948.2022.9789046
Bruno Canal, H. Klimach, S. Bampi, T. Balen
{"title":"Hybrid Comparator and Window Switching Scheme for low-power SAR ADC","authors":"Bruno Canal, H. Klimach, S. Bampi, T. Balen","doi":"10.1109/LASCAS53948.2022.9789046","DOIUrl":"https://doi.org/10.1109/LASCAS53948.2022.9789046","url":null,"abstract":"This work presents a SAR ADC architecture for low-voltage applications. The architecture combines a floating inverter pre-amplifier comparator, which uses the feedback bulk effect to operate with a low-voltage supply, and a voltage-to-time converter (VTC) to reduce comparator noise. Along with the VTC, a time-to-digital converter (TDC) assists the SAR procedure by applying a window switching scheme to save energy in the switching of the capacitive DAC (CDAC). The architecture is then compared to a traditional Vcm-based SAR ADC in a 28nm CMOS implementation, demonstrating that the proposed architecture can benefit the CDAC sizing due to improved CDAC linearity. Considering the power dissipated by the CDAC and the comparator, an ADC working with a 600mV power supply with 10MHz sample frequency achieves an improvement of 12% power dissipation considering a 12-bit ADC resolution.","PeriodicalId":356481,"journal":{"name":"2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128442979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
DMTJ-Based Non-Volatile Ternary Content Addressable Memory for Energy-Efficient High-Performance Systems 基于dmtj的高能效高性能系统非易失性三元内容可寻址存储器
2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS) Pub Date : 2022-03-01 DOI: 10.1109/LASCAS53948.2022.9789065
Kevin Vicuña, L. Prócel, L. Trojman, R. Taco
{"title":"DMTJ-Based Non-Volatile Ternary Content Addressable Memory for Energy-Efficient High-Performance Systems","authors":"Kevin Vicuña, L. Prócel, L. Trojman, R. Taco","doi":"10.1109/LASCAS53948.2022.9789065","DOIUrl":"https://doi.org/10.1109/LASCAS53948.2022.9789065","url":null,"abstract":"This paper explores performance of non-volatile ternary content addressable memories (NV-TCAMs), exploiting double-barrier magnetic tunnel junction (DMTJ) as comparatively evaluated with respect to the single barrier MTJ (SMTJ)-based solution. The comparison is performed at the circuit-level, considering different memory words. Overall, simulation results show that the DMTJ-based NV-TCAM is a good alternative to replace SMTJ-based NV-TCAM, mainly due to the search operation improvement. In particular, for a 144-bit NV-TCAM word operating at a nominal voltage of 1.1 V, the DMTJ-based solution offers improvements in terms of energy and search error rate of 14% and 66%, respectively, while showing similar search delay as the SMTJ-based NV-TCAM.","PeriodicalId":356481,"journal":{"name":"2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114932121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Implementation of a Fully Differential Low Noise Current Source for Fluxgate Sensors 磁通门传感器全差分低噪声电流源的实现
2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS) Pub Date : 2022-03-01 DOI: 10.1109/LASCAS53948.2022.9789061
Maximilian Scherzer, M. Auer, A. Valavanoglou, W. Magnes
{"title":"Implementation of a Fully Differential Low Noise Current Source for Fluxgate Sensors","authors":"Maximilian Scherzer, M. Auer, A. Valavanoglou, W. Magnes","doi":"10.1109/LASCAS53948.2022.9789061","DOIUrl":"https://doi.org/10.1109/LASCAS53948.2022.9789061","url":null,"abstract":"In this paper the implementation of a fully differ-ential low-noise current source is presented. It was designed to be used in the feedback path of a fluxgate magnetometer, however, the concept is applicable wherever a low noise and precise current is required. The current source is driven by a transimpedance amplifier that buffers the output of a current-steering DAC. To meet the mandatory precision as well as the required noise level a detailed analysis of the proposed circuit was carried out. The complete feedback path is integrated on chip using a 180 nm CMOS technology and occupies a total area of 2 mm2. The proposed design results in a signal-to-noise ratio of more than 104 dB for a bandwidth of 512 Hz, requiring only a supply voltage of 3.3 V. Moreover the current source is capable of driving currents of more than 18 mA into fluxgate sensors with an inductance of up to 9 mH while consuming 70 mW of power. To the best of the authors' knowledge the designed current source offers the best performance in terms of noise for fluxgate sensor front ends.","PeriodicalId":356481,"journal":{"name":"2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133965531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
22nm CMOS pW Standby Power Flip-Flops with/without Security using Dynamic Leakage Suppression Logic 采用动态泄漏抑制逻辑的22nm CMOS pW带/不带安全的备用电源触发器
2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS) Pub Date : 2022-03-01 DOI: 10.1109/LASCAS53948.2022.9789041
Duong Nghiep Huy, Guowei Chen, K. Niitsu
{"title":"22nm CMOS pW Standby Power Flip-Flops with/without Security using Dynamic Leakage Suppression Logic","authors":"Duong Nghiep Huy, Guowei Chen, K. Niitsu","doi":"10.1109/LASCAS53948.2022.9789041","DOIUrl":"https://doi.org/10.1109/LASCAS53948.2022.9789041","url":null,"abstract":"Two circuit designs of pW standby power flip-flop (FF) in 22nm ULL process, targeting low-voltage (down to 0.2V), and low-frequency IoT applications are presented. The proposed circuits are based on existing low-power FFs and Dynamic Leakage Suppression logic style [1]–[3]. Post-layout simulations of the proposed FFs in 22nm ULL show a standby power consumption of 0.46 and 0.55pW respectively at 0.2V, 0.5kHz maximum operating frequency. The performance can scale to 1V, 14kHz with 47/69pW standby power. The low standby power consumption and low voltage make the proposed circuits well-suited for small battery on-board or energy-harvested IoT devices. A design of low-power, low-frequency FF resistant to power analysis attacks utilizing the previous design and Secure Detect D-FF [4] is subsequently proposed.","PeriodicalId":356481,"journal":{"name":"2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129548378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
PPA Based CNN Architecture Explorer 基于PPA的CNN架构浏览器
2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS) Pub Date : 2022-03-01 DOI: 10.1109/LASCAS53948.2022.9789053
Masoud Shahshahani, D. Bhatia
{"title":"PPA Based CNN Architecture Explorer","authors":"Masoud Shahshahani, D. Bhatia","doi":"10.1109/LASCAS53948.2022.9789053","DOIUrl":"https://doi.org/10.1109/LASCAS53948.2022.9789053","url":null,"abstract":"Field-Programmable Gate Arrays (FPGAs) are becoming increasingly popular for implementing convolutional neural networks (CNNs) due to their low latency and high energy efficiency. In practice, a software designer first explores various CNN architectures in software to improve architecture's validation accuracy. Once an architecture is finalized, the designer must build a computation core on an FPGA for inference acceleration. The requirement of FPGA Performance, Power consumption, and Area (or resources) (PPA) is affected by many CNN model parameters, accelerator topology, and classification accuracy for a CNN implementation. However, the CNN mapping design space is enormous, and efficient mapping of CNN can quickly become a challenging task. Therefore, an exploration tool is essential for building a reconfigurable, fast, and efficient hardware accelerator. We have presented an integrated methodology for exploring FPGA-based CNN architectures by making tradeoffs between the performance, power, and area. This methodology becomes a mapping aid for software engineers who can evaluate the effect of CNN design on the implementation and performance of FPGA-based CNN accelerators.","PeriodicalId":356481,"journal":{"name":"2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122280968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Exploring the Impacts of Multiple Kernel Sizes of Gaussian Filters Combined to Approximate Computing in Canny Edge Detection 探讨多核大小高斯滤波器结合近似计算对边缘检测的影响
2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS) Pub Date : 2022-03-01 DOI: 10.1109/LASCAS53948.2022.9789080
M. Monteiro, Ismael Seidel, M. Grellert, José Luís Almada Güntzel, L. Soares, C. Meinhardt
{"title":"Exploring the Impacts of Multiple Kernel Sizes of Gaussian Filters Combined to Approximate Computing in Canny Edge Detection","authors":"M. Monteiro, Ismael Seidel, M. Grellert, José Luís Almada Güntzel, L. Soares, C. Meinhardt","doi":"10.1109/LASCAS53948.2022.9789080","DOIUrl":"https://doi.org/10.1109/LASCAS53948.2022.9789080","url":null,"abstract":"Image processing applications are currently available on mobile devices, stressing the energy efficiency demands during the hardware design. In these applications, image edge detectors use filters as a preprocessing step to reduce undesirable artifacts and smooth the image. This work explores the combination of Multiplierless Multiple Constant Multiplication and Approximate Computing techniques on the Gaussian filter, investigating three different kernel size impacts on image processing. The impact of approximation is evaluated at different levels using the copy strategy technique on the LSBs of adders. The results show power and area reductions for the kernel sizes under evaluation. For instance, the approximate kernel $7times 7$ kernel achieved reductions of up to 40% and 48% for the area and power consumption, respectively, compared to the exact version. It shows ample space for design exploration targeting different trade-offs of quality and power results.","PeriodicalId":356481,"journal":{"name":"2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127964958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Voltage and Technology Scaling of DMTJ-based STT-MRAMs for Energy-Efficient Embedded Memories 节能嵌入式存储器中基于dmtj的stt - mram的电压和技术缩放
2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS) Pub Date : 2022-03-01 DOI: 10.1109/LASCAS53948.2022.9789054
Esteban Garzón, R. Taco, L. Prócel, L. Trojman, M. Lanuzza
{"title":"Voltage and Technology Scaling of DMTJ-based STT-MRAMs for Energy-Efficient Embedded Memories","authors":"Esteban Garzón, R. Taco, L. Prócel, L. Trojman, M. Lanuzza","doi":"10.1109/LASCAS53948.2022.9789054","DOIUrl":"https://doi.org/10.1109/LASCAS53948.2022.9789054","url":null,"abstract":"This work presents energy advantages allowed by the technology and voltage scaling of spin-transfer torque mag-netic random access memories (STT-MRAMs) based on perpen-dicular double-barrier magnetic tunnel junction (DMTJ), with two reference layers. DMTJ is benchmarked against the single-barrier MTJ (SMTJ) -based alternative, and a comprehensive evaluation is carried out through a cross-layer simulation frame-work, considering state-of-the-art Verilog-A based SMTJ and DMTJ compact models, along with a 0.8V FinFET technology. Simulation results show that, thanks to the lower voltage op-erating point, DMTJ-based STT-MRAM allows energy savings for write/read operations of about 38%/45%, as compared to its SMTJ-based counterpart. Moreover, scaling from the 28 nm down to the 20 nm node, the DMTJ-based memory cell improves write/read energy of about 29%/33% at the expense of longer access times.","PeriodicalId":356481,"journal":{"name":"2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125556545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Sensor Systems for Smart Agriculture 智能农业传感器系统
2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS) Pub Date : 2022-03-01 DOI: 10.1109/LASCAS53948.2022.9789078
D. Barrettino
{"title":"Sensor Systems for Smart Agriculture","authors":"D. Barrettino","doi":"10.1109/LASCAS53948.2022.9789078","DOIUrl":"https://doi.org/10.1109/LASCAS53948.2022.9789078","url":null,"abstract":"This paper presents two sensor systems used in smart agriculture. The first sensor system is capable of remote monitoring at real time the condition of grains stored in silo bags. The second sensor system comprises soil's nitrogen (N), potassium (K), phosphorus (P) and pH sensors to optimize at real-time the precise application of fertilizers. The details about the design and fabrication of these sensor systems together with some experimental results obtained during field tests are reported.","PeriodicalId":356481,"journal":{"name":"2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125743043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Novel Event-Based Method for ASK Demodulation 一种基于事件的ASK解调方法
2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS) Pub Date : 2022-03-01 DOI: 10.1109/LASCAS53948.2022.9789085
Alexis Rodrigo Iga Jadue, S. Engels, L. Fesquet
{"title":"A Novel Event-Based Method for ASK Demodulation","authors":"Alexis Rodrigo Iga Jadue, S. Engels, L. Fesquet","doi":"10.1109/LASCAS53948.2022.9789085","DOIUrl":"https://doi.org/10.1109/LASCAS53948.2022.9789085","url":null,"abstract":"This paper presents a novel ASK demodulation technique, using an Event-Based ADC (EB-ADC) and a digital ASK demodulation algorithm. The EB-ADC employs a minimalist Level Crossing Sample Scheme (LCSS) with only 2 levels, and uses a Time-to-Digital Converter (TDC) for measuring the time elapsed between two consecutive level crossings (events). The level crossing detection modules are composed of two strong-arm comparators. These comparators were characterized through an electrical simulation and then modeled in SystemVerilog in order to be integrated in a full digital simulation environment. The RF input signal of the testbench and its noise model have been modeled by replicating python's awgn function of commpy library. This demodulation technique takes advantage of the time measurement elapsed between two adjacent events, to apply a digital demodulation algorithm, for improving the symbol recognition performance and the noise resiliency, reaching for example a $text{BER}=3.33cdot 10^{-7}$ with a modulation index of 10%, a bit rate of 6.78 Mbps and a SNR of 16 dB. A circuit implementing this approach is currently in fabrication in FDSOI 28nm STMicroelectronics technology.","PeriodicalId":356481,"journal":{"name":"2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)","volume":"146 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123366395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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