22nm CMOS pW Standby Power Flip-Flops with/without Security using Dynamic Leakage Suppression Logic

Abstract

Two circuit designs of pW standby power flip-flop (FF) in 22nm ULL process, targeting low-voltage (down to 0.2V), and low-frequency IoT applications are presented. The proposed circuits are based on existing low-power FFs and Dynamic Leakage Suppression logic style [1]–[3]. Post-layout simulations of the proposed FFs in 22nm ULL show a standby power consumption of 0.46 and 0.55pW respectively at 0.2V, 0.5kHz maximum operating frequency. The performance can scale to 1V, 14kHz with 47/69pW standby power. The low standby power consumption and low voltage make the proposed circuits well-suited for small battery on-board or energy-harvested IoT devices. A design of low-power, low-frequency FF resistant to power analysis attacks utilizing the previous design and Secure Detect D-FF [4] is subsequently proposed.