Hybrid Comparator and Window Switching Scheme for low-power SAR ADC

Abstract

This work presents a SAR ADC architecture for low-voltage applications. The architecture combines a floating inverter pre-amplifier comparator, which uses the feedback bulk effect to operate with a low-voltage supply, and a voltage-to-time converter (VTC) to reduce comparator noise. Along with the VTC, a time-to-digital converter (TDC) assists the SAR procedure by applying a window switching scheme to save energy in the switching of the capacitive DAC (CDAC). The architecture is then compared to a traditional Vcm-based SAR ADC in a 28nm CMOS implementation, demonstrating that the proposed architecture can benefit the CDAC sizing due to improved CDAC linearity. Considering the power dissipated by the CDAC and the comparator, an ADC working with a 600mV power supply with 10MHz sample frequency achieves an improvement of 12% power dissipation considering a 12-bit ADC resolution.