Voltage and Technology Scaling of DMTJ-based STT-MRAMs for Energy-Efficient Embedded Memories

Abstract

This work presents energy advantages allowed by the technology and voltage scaling of spin-transfer torque mag-netic random access memories (STT-MRAMs) based on perpen-dicular double-barrier magnetic tunnel junction (DMTJ), with two reference layers. DMTJ is benchmarked against the single-barrier MTJ (SMTJ) -based alternative, and a comprehensive evaluation is carried out through a cross-layer simulation frame-work, considering state-of-the-art Verilog-A based SMTJ and DMTJ compact models, along with a 0.8V FinFET technology. Simulation results show that, thanks to the lower voltage op-erating point, DMTJ-based STT-MRAM allows energy savings for write/read operations of about 38%/45%, as compared to its SMTJ-based counterpart. Moreover, scaling from the 28 nm down to the 20 nm node, the DMTJ-based memory cell improves write/read energy of about 29%/33% at the expense of longer access times.