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2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)最新文献

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On the Netlist Gate-level Pruning for Tree-based Machine Learning Accelerators
2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS) Pub Date : 2022-03-01 DOI: 10.1109/LASCAS53948.2022.9789043
B. Abreu, Guilherme Paim, Jorge Castro-Godínez, M. Grellert, S. Bampi
{"title":"On the Netlist Gate-level Pruning for Tree-based Machine Learning Accelerators","authors":"B. Abreu, Guilherme Paim, Jorge Castro-Godínez, M. Grellert, S. Bampi","doi":"10.1109/LASCAS53948.2022.9789043","DOIUrl":"https://doi.org/10.1109/LASCAS53948.2022.9789043","url":null,"abstract":"The technology advances in the recent years have led to the spread use of Machine Learning (ML) models in embedded systems. Due to the battery limitations of such edge devices, energy consumption has become a major problem. Tree-based models, such as Decision Trees (DTs) and Random Forests (RFs), are well-known ML tools that provide higher than standard accuracy results for several tasks. These tools are convenient for battery-powered devices due to their simplicity, and they can be further optimized with approximate computing techniques. This paper explores gate-level pruning for DTs and RFs. By using a framework that generates VLSI descriptions of the ML models, we investigate gate-level pruning to the mapped netlist generated after logic synthesis for three case studies. Several analyses on the energy- and area-accuracy trade-offs were performed and we found that we can obtain significant energy and area savings for small or even negligible accuracy drops, which indicates that pruning techniques can be applied to optimize tree-based hardware implementations.","PeriodicalId":356481,"journal":{"name":"2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115794074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
TISIRC: A multichannel ASIC with gain control for SiPM detectors TISIRC:用于SiPM检测器的多通道增益控制ASIC
2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS) Pub Date : 2022-03-01 DOI: 10.1109/LASCAS53948.2022.9789074
R. Barraza, Angel Abusleme, S. Kuleshov
{"title":"TISIRC: A multichannel ASIC with gain control for SiPM detectors","authors":"R. Barraza, Angel Abusleme, S. Kuleshov","doi":"10.1109/LASCAS53948.2022.9789074","DOIUrl":"https://doi.org/10.1109/LASCAS53948.2022.9789074","url":null,"abstract":"SiPM/MPPC are detectors that give a signal when a single photon hits them. To read those detectors circuits must, on the one hand, be fast enough to capture the signals, and on the other hand, manage the detector capacitance. Also, they must deal with SiPM gain variations depending on external variables, and read the complete range of fired pixels. This work aims to design and tape-out a SiPM readout chip that reads high-capacitance SiPMs with up to 3000 pixels and to control their gain. To achieve those objectives, a 4 channel chip was designed using a 180 nm CMOS technology, with bias voltage control of each detector to adjust their gains. The integrated circuit called TISIRC was designed, simulated, fabricated, and soon it will be tested.","PeriodicalId":356481,"journal":{"name":"2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117038250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Highly Compact 1W Ku-Band Power Amplifier 一种高度紧凑的1W ku波段功率放大器
2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS) Pub Date : 2022-03-01 DOI: 10.1109/LASCAS53948.2022.9789049
B. Coquillas, E. Kerhervé, Anne-Charlotte Amiaud, L. Roussel, S. Redois, B. Louis, T. Merlet, V. Petit
{"title":"A Highly Compact 1W Ku-Band Power Amplifier","authors":"B. Coquillas, E. Kerhervé, Anne-Charlotte Amiaud, L. Roussel, S. Redois, B. Louis, T. Merlet, V. Petit","doi":"10.1109/LASCAS53948.2022.9789049","DOIUrl":"https://doi.org/10.1109/LASCAS53948.2022.9789049","url":null,"abstract":"This paper presents a highly compact double-balanced two-stage Ku-Band SiGe power amplifier. Four power cells are combined in a balanced architecture which occupies less than 2mm2. As a proof of concept, the power amplifier was designed with a 0.13-μm SiGe BiCMOS technology. The simulated performances at 18GHz exhibit a saturated power higher than 30dBm up to 90°C, a linear gain of 21.2dB and a peak power added efficiency of 26.5%.","PeriodicalId":356481,"journal":{"name":"2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)","volume":"185 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123737711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Optimized Hardware Implementation of Vedic Binary Multiplier using Nikhilam Sutra on FPGA 基于Nikhilam经的吠陀二进制乘法器的FPGA优化硬件实现
2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS) Pub Date : 2022-03-01 DOI: 10.1109/LASCAS53948.2022.9789063
Pal Yash, M. Thakare, Babita Jajodia
{"title":"Optimized Hardware Implementation of Vedic Binary Multiplier using Nikhilam Sutra on FPGA","authors":"Pal Yash, M. Thakare, Babita Jajodia","doi":"10.1109/LASCAS53948.2022.9789063","DOIUrl":"https://doi.org/10.1109/LASCAS53948.2022.9789063","url":null,"abstract":"This paper proposes an efficient and optimized method of binary multiplication based on Nikhilam Sutra (algo-rithm) of Ancient Vedic Mathematics feasible for practical and real-time hardware implementations. This work demonstrates hardware implementation results of varying input bit-lengths (4-bit, 8-bit, 16-bit, 32-bit, and 64-bit) on Field Programmable Gate Array (FPGA) platform with an advantage of the reduced combinational delay and low device utilization (no. of slice LUTs) over existing alternative multiplication units and state-of-the-art Urdhva Tiriyakbhyam and Nikhilam Sutra-based multiplication architectures. The proposed binary multiplier architecture is also demonstrated on the Virtex-7 (xc7vx485t-3ffg1157) FPGA device. Hardware implementation results on Xilinx Virtex-7 FPGA device for 8 × 8 proposed multiplication unit show that the design consumes 24 slice LUTs and maximum frequency up to 257.1 MHz.","PeriodicalId":356481,"journal":{"name":"2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129013729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Phase Space Reconstruction Based Real Time Fatigue Crack Growth Estimation for Structural Health Monitoring Ships 基于相空间重构的结构健康监测船舶疲劳裂纹扩展实时估计
2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS) Pub Date : 2022-03-01 DOI: 10.1109/LASCAS53948.2022.9789050
P. Bhange, D. Joshi, A. Acharyya, Sunil Kumar Pandu, K. Mankari, S. G. Acharyya, K. Sridhar
{"title":"Phase Space Reconstruction Based Real Time Fatigue Crack Growth Estimation for Structural Health Monitoring Ships","authors":"P. Bhange, D. Joshi, A. Acharyya, Sunil Kumar Pandu, K. Mankari, S. G. Acharyya, K. Sridhar","doi":"10.1109/LASCAS53948.2022.9789050","DOIUrl":"https://doi.org/10.1109/LASCAS53948.2022.9789050","url":null,"abstract":"A real time estimation of crack growth rate oc-curring in a high strength low alloy DMR 249A steel in an in-situ acoustic emission monitoring setup for fatigue crack propagation was done. This investigation was carried out for structural health monitoring of ships where compact tension specimen was subjected to real sea state condition with sea state value of 4. The work focuses on building a relationship between crack growth rate and acoustic emission signal acquired from acoustic emission sensors. A methodology which could predict the degradation occurring in ship steel when subjected to fatigue load was developed. In this regard, a phase space reconstruction based methodology has been introduced which could predict the crack growth rate in this material with an accuracy of 95%.","PeriodicalId":356481,"journal":{"name":"2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130625956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Novel Single Lead to 12-Lead ECG Reconstruction Methodology Using Convolutional Neural Networks and LSTM 一种基于卷积神经网络和LSTM的单导联到12导联心电图重构方法
2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS) Pub Date : 2022-03-01 DOI: 10.1109/LASCAS53948.2022.9789045
Vishnuvardhan Gundlapalle, A. Acharyya
{"title":"A Novel Single Lead to 12-Lead ECG Reconstruction Methodology Using Convolutional Neural Networks and LSTM","authors":"Vishnuvardhan Gundlapalle, A. Acharyya","doi":"10.1109/LASCAS53948.2022.9789045","DOIUrl":"https://doi.org/10.1109/LASCAS53948.2022.9789045","url":null,"abstract":"The Electrocardiogram (ECG) is a useful diagnostic tool to diagnose cardiovascular diseases (CVD). Standard 12-Lead ECG setup is most commonly used by doctors for the diagnosis. But the promising type of wearable ECG device uses minimal wire setup on the body to increase patients' comfort resulting in fewer recorded leads, mainly single lead. There is a need to reconstruct the remaining leads from these less recorded leads. Accounting for this, we are proposing a novel Single Lead to 12-Lead ECG reconstruction methodology using convolution neural networks (CNN) and long short term memory (LSTM). In the proposed methodology, lead-II is taken as the basis lead to reconstruct the remaining independent leads (I, V1, V2, V3, V4, V5, and V6). Seven individual models corresponding to the above mentioned seven independent leads have been trained, where each model takes lead-II as input and gives I/V1/V2/V3/V4/V5/V6 as output. Leads III, aVR, aVL, and aVF are reconstructed using a standard approach using original lead II and reconstructed lead I signals, without the need for deep learning models. The proposed methodology was evaluated on myocardial infarction data from PTBDB using R2 statistics, correlation coefficient, and regression coefficient. The mean values averaged across all the 11 leads of the stated performance metrics obtained were 93.62%, 0.973, and 0.959, respectively.","PeriodicalId":356481,"journal":{"name":"2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133450318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
MAx-DNN: Multi-Level Arithmetic Approximation for Energy-Efficient DNN Hardware Accelerators 高效DNN硬件加速器的多级算法近似
2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS) Pub Date : 2022-03-01 DOI: 10.1109/LASCAS53948.2022.9789055
Vasileios Leon, Georgios Makris, S. Xydis, K. Pekmestzi, D. Soudris
{"title":"MAx-DNN: Multi-Level Arithmetic Approximation for Energy-Efficient DNN Hardware Accelerators","authors":"Vasileios Leon, Georgios Makris, S. Xydis, K. Pekmestzi, D. Soudris","doi":"10.1109/LASCAS53948.2022.9789055","DOIUrl":"https://doi.org/10.1109/LASCAS53948.2022.9789055","url":null,"abstract":"Nowadays, the rapid growth of Deep Neural Network (DNN) architectures has established them as the defacto approach for providing advanced Machine Learning tasks with excellent accuracy. Targeting low-power DNN computing, this paper examines the interplay of fine-grained error resilience of DNN workloads in collaboration with hardware approximation techniques, to achieve higher levels of energy efficiency. Utilizing the state-of-the-art ROUP approximate multipliers, we systematically explore their fine-grained distribution across the network according to our layer-, filter-, and kernel-level approaches, and examine their impact on accuracy and energy. We use the ResNet-8 model on the CIFAR-10 dataset to evaluate our approximations. The proposed solution delivers up to 54% energy gains in exchange for up to 4% accuracy loss, compared to the baseline quantized model, while it provides 2 × energy gains with better accuracy versus the state-of-the-art DNN approximations.","PeriodicalId":356481,"journal":{"name":"2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117095243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Fast Approximate Function Generation Method to ATMR Architecture ATMR结构的快速近似函数生成方法
2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS) Pub Date : 2022-03-01 DOI: 10.1109/LASCAS53948.2022.9789047
Guilherme B. Manske, Clayton R. Farias, P. Butzen, L. Rosa
{"title":"A Fast Approximate Function Generation Method to ATMR Architecture","authors":"Guilherme B. Manske, Clayton R. Farias, P. Butzen, L. Rosa","doi":"10.1109/LASCAS53948.2022.9789047","DOIUrl":"https://doi.org/10.1109/LASCAS53948.2022.9789047","url":null,"abstract":"Transistor miniaturization produces circuits with higher transistor density, allowing the development of more complex circuits. On the other hand, the circuit susceptibility to faults is increasing. The Triple Modular Redundancy with a majority voter presents a 100% fault coverage for single faults in the modules, but it has more than 200% of area overhead. Approximate computing is used to create Approximate Triple Modular Redundancy (ATMR) modules, reducing area overhead. This work proposes a fast method to obtain approximate modules for an ATMR architecture. This is done using variables with the highest correlation with the output to create approximate solutions. The generated ATMRs have in the best case an area overhead of 86% and an error rate of 3.6%. Our method generates ATMR functions 7 orders of magnitude faster on average when compared to [1]. Therefore, the proposed method presents higher scalability capable of embracing higher complex-ity designs. The low computational cost of finding the solutions is key to turning feasible using ATMR in complex designs.","PeriodicalId":356481,"journal":{"name":"2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)","volume":"479 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116167229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Near threshold pulse transit time processor for central blood pressure estimation 用于中心血压估计的近阈值脉冲传递时间处理器
2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS) Pub Date : 2022-03-01 DOI: 10.1109/LASCAS53948.2022.9789076
Francisco Veirano, Pablo Pérez-Nicoli, Nicolás Gammarano, G. Fierro, Fernando Silveira
{"title":"Near threshold pulse transit time processor for central blood pressure estimation","authors":"Francisco Veirano, Pablo Pérez-Nicoli, Nicolás Gammarano, G. Fierro, Fernando Silveira","doi":"10.1109/LASCAS53948.2022.9789076","DOIUrl":"https://doi.org/10.1109/LASCAS53948.2022.9789076","url":null,"abstract":"In this work a digital peripheral that can measure pulse transit time for central blood pressure estimation is presented. To do so, it processes ECG and BCG signals in real time by detecting the R-waves in the ECG and using this as time reference for measuring intervals of interest such as RJ, IJ and RR. The circuit was fabricated in a 180 nm process and experimental results are presented. The peripheral works at the near-threshold region and consumes 7 pJ/cycle with 0.43 V of supply voltage while operating at 8 kHz. We showed that state of the art performance can be achieved in the processing required for wearable estimation of central blood pressure while operating the digital circuit in the near-threshold region.","PeriodicalId":356481,"journal":{"name":"2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)","volume":"165 5 Pt 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123254668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Notch Frequency Generation Methods in Noise Spread Spectrum for Pulse Coding Switching DC-DC Converter 脉冲编码开关DC-DC变换器噪声扩频中的陷波频率生成方法
2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS) Pub Date : 2022-03-01 DOI: 10.1109/LASCAS53948.2022.9789057
Gui-Yi Dong, Shogo Katayama, Yifei Sun, Y. Kobori, A. Kuwana, Haruo Kobayashi
{"title":"Notch Frequency Generation Methods in Noise Spread Spectrum for Pulse Coding Switching DC-DC Converter","authors":"Gui-Yi Dong, Shogo Katayama, Yifei Sun, Y. Kobori, A. Kuwana, Haruo Kobayashi","doi":"10.1109/LASCAS53948.2022.9789057","DOIUrl":"https://doi.org/10.1109/LASCAS53948.2022.9789057","url":null,"abstract":"This paper introduces two pulse coding control methods for generating notch frequency automatically in noise spread spectrum for switching DC-DC converters; these are based on our previously proposed method. Our two methods here generate the notch frequency Fn automatically according to the received frequency Fin. The first one is a constant frequency PWM-controlled buck DC-DC converter where the clock frequency and coding pulse width are automatically set according to the frequency of the received signal to generate notch characteristics. The second one is a pulse frequency modulation (PFM) pulse coding DC-DC converter which generates a composite notch characteristic where both the constant pulse width and the periodic modulation coding pulse width are automatically matched with input frequency Fin. Our simulation results show that the transient response is fast and the output voltage overshoot is small.","PeriodicalId":356481,"journal":{"name":"2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128682076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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