Optimized Hardware Implementation of Vedic Binary Multiplier using Nikhilam Sutra on FPGA

Abstract

This paper proposes an efficient and optimized method of binary multiplication based on Nikhilam Sutra (algo-rithm) of Ancient Vedic Mathematics feasible for practical and real-time hardware implementations. This work demonstrates hardware implementation results of varying input bit-lengths (4-bit, 8-bit, 16-bit, 32-bit, and 64-bit) on Field Programmable Gate Array (FPGA) platform with an advantage of the reduced combinational delay and low device utilization (no. of slice LUTs) over existing alternative multiplication units and state-of-the-art Urdhva Tiriyakbhyam and Nikhilam Sutra-based multiplication architectures. The proposed binary multiplier architecture is also demonstrated on the Virtex-7 (xc7vx485t-3ffg1157) FPGA device. Hardware implementation results on Xilinx Virtex-7 FPGA device for 8 × 8 proposed multiplication unit show that the design consumes 24 slice LUTs and maximum frequency up to 257.1 MHz.