On the Netlist Gate-level Pruning for Tree-based Machine Learning Accelerators

Abstract

The technology advances in the recent years have led to the spread use of Machine Learning (ML) models in embedded systems. Due to the battery limitations of such edge devices, energy consumption has become a major problem. Tree-based models, such as Decision Trees (DTs) and Random Forests (RFs), are well-known ML tools that provide higher than standard accuracy results for several tasks. These tools are convenient for battery-powered devices due to their simplicity, and they can be further optimized with approximate computing techniques. This paper explores gate-level pruning for DTs and RFs. By using a framework that generates VLSI descriptions of the ML models, we investigate gate-level pruning to the mapped netlist generated after logic synthesis for three case studies. Several analyses on the energy- and area-accuracy trade-offs were performed and we found that we can obtain significant energy and area savings for small or even negligible accuracy drops, which indicates that pruning techniques can be applied to optimize tree-based hardware implementations.