Full System Exploration of On-Chip Wireless Communication on Many-Core Architectures

In order to develop sustainable and more powerful information technology (IT) infrastructures, the challenges posed by the “memory wall” are critical for the design of high-performance and high-efficiency many-core computing systems. In this context, recent advances in the integration of nano-antennas, enabling novel short-distance communication paradigms, promise disruptive gains. To gauge their potential benefit for the next-generation of many-core server designs, it is crucial to explore the impact of wireless communication links from a whole-system viewpoint, considering complex architectures and applications characteristics. To this end, in this work we introduce an extension to the popular gem5 full system-level simulator, enabling the simulation of many-core platforms featuring on-chip wireless channels. This new extension allows the flexible investigation of different combinations of wireless and wired interconnects, as well as diverse connection protocols. We showcase its capabilities by performing an architectural exploration, targeting a multi-core system executing image inference using an AlexNet Neural Network benchmark. A 2.3x speedup is obtained when implementing wireless communication between cores instead of traditional on-chip wired interconnects.