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IEEE 1995 International Integrated Reliability Workshop. Final Report最新文献

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A system engineering approach to the design of on-chip electrostatic discharge protection 片上静电放电保护设计的系统工程方法
IEEE 1995 International Integrated Reliability Workshop. Final Report Pub Date : 1995-10-22 DOI: 10.1109/IRWS.1995.493570
J. Eaton, R. Horner
{"title":"A system engineering approach to the design of on-chip electrostatic discharge protection","authors":"J. Eaton, R. Horner","doi":"10.1109/IRWS.1995.493570","DOIUrl":"https://doi.org/10.1109/IRWS.1995.493570","url":null,"abstract":"Customer demands for increased ESD protection of CMOS integrated circuit chips and for process enhancements that increase performance but weaken transistors combine to create an important engineering challenge for chip designers. Our objective was to find a common protection solution applicable to the majority of our custom and semicustom chips, using a high profile chip as a design vehicle. This paper describes the development of a technique for quantitative prediction of chip survival (and failure) when stressed according to the Human Body Model. It also describes the development of a design review process to screen weak designs. Careful analyses of successful, unsuccessful and enhanced chip layouts as systems of current paths plus utilization of normal circuit components provide the key ingredients.","PeriodicalId":355898,"journal":{"name":"IEEE 1995 International Integrated Reliability Workshop. Final Report","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133556974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Simulation of wafer scale diagnosis 晶圆规模诊断模拟
IEEE 1995 International Integrated Reliability Workshop. Final Report Pub Date : 1995-10-22 DOI: 10.1109/IRWS.1995.493600
A. Iychettira, L. LaForge
{"title":"Simulation of wafer scale diagnosis","authors":"A. Iychettira, L. LaForge","doi":"10.1109/IRWS.1995.493600","DOIUrl":"https://doi.org/10.1109/IRWS.1995.493600","url":null,"abstract":"Summary form only given. DWI (Diagnosis of Wafer Scale Integrated Circuits), is a DOS C/sup ++/ program whose purpose is to assess the practicality of system-level diagnosis on a wafer scale. On the manufacturing line, diagnosis offers a replacement for probe test. For in-the-field operation, diagnosis holds promise for increasing the accuracy whereby faulty elements are identified, at reduced cost. With all of these applications, diagnosis eliminates or greatly reduces the need of external test equipment. The increasing prevalence of monolithic and multichip wafer scale modules may accelerate the search for alternatives to probe and scan. DWI can help the designer answer architectural questions such as: 1) What is the effect of the element failure rate and distribution of failures? 2) What is the best diagnosis algorithm?.","PeriodicalId":355898,"journal":{"name":"IEEE 1995 International Integrated Reliability Workshop. Final Report","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121239201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Implementation of a WLR-program into a production line 在生产线上实施wlr程序
IEEE 1995 International Integrated Reliability Workshop. Final Report Pub Date : 1995-10-22 DOI: 10.1109/IRWS.1995.493575
A. Papp, F. Bieringer, D. Koch, H. Kammer, A. Kohlhase, A. Lill, A. Preussger, A. Schlemm, M. Schneegans
{"title":"Implementation of a WLR-program into a production line","authors":"A. Papp, F. Bieringer, D. Koch, H. Kammer, A. Kohlhase, A. Lill, A. Preussger, A. Schlemm, M. Schneegans","doi":"10.1109/IRWS.1995.493575","DOIUrl":"https://doi.org/10.1109/IRWS.1995.493575","url":null,"abstract":"Describes the implementation of a process reliability monitoring program on the basis of wafer level tests into the control concept of a production line. For the main reliability parameters-gate oxide integrity, hot carrier injection immunity and metallization stability against electromigration-the methods, test structures, test conditions and results are presented. Some examples for reliability improvement and the future targets of the WLR-program are given.","PeriodicalId":355898,"journal":{"name":"IEEE 1995 International Integrated Reliability Workshop. Final Report","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126059893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Reliability prediction through critical area analysis 通过临界区分析进行可靠性预测
IEEE 1995 International Integrated Reliability Workshop. Final Report Pub Date : 1995-10-22 DOI: 10.1109/IRWS.1995.493604
J.H.N. Mattick, R. Kelsall, R. Miles
{"title":"Reliability prediction through critical area analysis","authors":"J.H.N. Mattick, R. Kelsall, R. Miles","doi":"10.1109/IRWS.1995.493604","DOIUrl":"https://doi.org/10.1109/IRWS.1995.493604","url":null,"abstract":"Critical Area (CA) analysis can be applied to the prediction of post-fabrication reliability of integrated circuits. However, the accuracy of the prediction is dependent on the validity of the chosen defect model. A comparison, highlighting the importance of this selection, is made between the results obtained using two differently shaped models. In conclusion, a novel CA analysis technique is outlined, which provides both quick and accurate computation of layout CA.","PeriodicalId":355898,"journal":{"name":"IEEE 1995 International Integrated Reliability Workshop. Final Report","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131057609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Stepped current stressing of line/stud structures 线/螺柱结构的阶梯电流应力
IEEE 1995 International Integrated Reliability Workshop. Final Report Pub Date : 1995-10-22 DOI: 10.1109/IRWS.1995.493589
S. Yankee, D. Bouldin
{"title":"Stepped current stressing of line/stud structures","authors":"S. Yankee, D. Bouldin","doi":"10.1109/IRWS.1995.493589","DOIUrl":"https://doi.org/10.1109/IRWS.1995.493589","url":null,"abstract":"We have used stepped-current stressing to look at the stability of refractory liners used in Al-based interconnects. These redundancy layers play a critical role in the reliability of Al-based interconnects by allowing current flow even when the Al portion of the line is damaged by electromigration or stress migration. For this work, we have used line/stud structures, both as-received and previously damaged, and analyzed results with respect to a simple model that describes temperature increase in terms of material properties and thermal conduction. We discuss the difference in behavior of damaged and undamaged lines, the temperature associated with failure, and the implications for current-limit design rules.","PeriodicalId":355898,"journal":{"name":"IEEE 1995 International Integrated Reliability Workshop. Final Report","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122267309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Wafer level reliability procedures to monitor gate oxide quality using V ramp and J ramp test methodology 使用V坡道和J坡道测试方法监测栅极氧化物质量的晶圆级可靠性程序
IEEE 1995 International Integrated Reliability Workshop. Final Report Pub Date : 1995-10-22 DOI: 10.1109/IRWS.1995.493584
L. Lie, A. Kapoor
{"title":"Wafer level reliability procedures to monitor gate oxide quality using V ramp and J ramp test methodology","authors":"L. Lie, A. Kapoor","doi":"10.1109/IRWS.1995.493584","DOIUrl":"https://doi.org/10.1109/IRWS.1995.493584","url":null,"abstract":"Comparison between voltage ramp and current ramp test methods in detecting low level oxide defects is presented. Besides test conditions, such as voltage or current ramp rate, initial stress voltage or current density, gate oxide area, which are already known to be determining factors, several other factors are shown in this paper to impact defect density as measured by J ramp and V ramp test methods. These factors are: gate oxide thickness, test structure layout, types of test structures, and wafer processing.","PeriodicalId":355898,"journal":{"name":"IEEE 1995 International Integrated Reliability Workshop. Final Report","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114213667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Statistical reliability prediction 统计可靠性预测
IEEE 1995 International Integrated Reliability Workshop. Final Report Pub Date : 1995-10-22 DOI: 10.1109/IRWS.1995.493598
D. Gibson
{"title":"Statistical reliability prediction","authors":"D. Gibson","doi":"10.1109/IRWS.1995.493598","DOIUrl":"https://doi.org/10.1109/IRWS.1995.493598","url":null,"abstract":"An analysis technique is presented which allows the construction of a statistical model of device lifetime given data obtained from traditional reliability life testing. Unlike techniques presently used, this method does not require that each life test be completed to a high percentage failure, produces a model whose accuracy is quantifiable, and can predict expected times to failure at percentages other than 50%. Confidence and prediction intervals can be calculated around all model parameters (such as activation energy), all performance parameters (such as estimated median time to failure, MTF), and individual performance predictions (estimated times-to-failure, TTF). This procedure is demonstrated using the electromigration failure mechanism, but can be applied to any failure model.","PeriodicalId":355898,"journal":{"name":"IEEE 1995 International Integrated Reliability Workshop. Final Report","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123902201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
On the road to building-in reliability 在建立可靠性的道路上
IEEE 1995 International Integrated Reliability Workshop. Final Report Pub Date : 1995-10-22 DOI: 10.1109/IRWS.1995.493567
D. L. Erhart, H. Schafft, W. K. Gladden
{"title":"On the road to building-in reliability","authors":"D. L. Erhart, H. Schafft, W. K. Gladden","doi":"10.1109/IRWS.1995.493567","DOIUrl":"https://doi.org/10.1109/IRWS.1995.493567","url":null,"abstract":"The cycle-time pressures to reduce the time required to introduce new products, and the continued demands for decreasing product failure rates are pushing our existing reliability risk management methodology to its limits. These issues have stimulated the reassessment of our strategy and the development of an alternate approach. In this presentation, we explore the implementation of building-in reliability (BIR). We develop working definitions for BIR and the present reliability risk assessment methodology, testing-in reliability (TIR). We contrast the TIR and BIR approaches in the context of a new product introduction (NPI) process, as well as in the context of day-to-day manufacturing. We examine the TIR and BIR approaches to metallization reliability, and develop a straw man proposal for the implementation of BIR.","PeriodicalId":355898,"journal":{"name":"IEEE 1995 International Integrated Reliability Workshop. Final Report","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125544729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Detection and measurement of hot carrier degradation associated with asymmetric p-channel transistors 非对称p沟道晶体管热载流子退化的检测与测量
IEEE 1995 International Integrated Reliability Workshop. Final Report Pub Date : 1995-10-22 DOI: 10.1109/IRWS.1995.493578
B. Aldridge, N. Sharif, E. Yum, F. Serhan
{"title":"Detection and measurement of hot carrier degradation associated with asymmetric p-channel transistors","authors":"B. Aldridge, N. Sharif, E. Yum, F. Serhan","doi":"10.1109/IRWS.1995.493578","DOIUrl":"https://doi.org/10.1109/IRWS.1995.493578","url":null,"abstract":"Control and monitoring of the manufacturing process is essential in the production of reliable devices. A recent experience involving the LDD implant of a 0.91-/spl mu/m CMOS process resulted in asymmetric p-channel transistors with spatially dependent hot carrier performance. This event is especially significant because the monitoring in place could have easily missed the degradation in reliability due to the layout dependence of the test structures. This paper presents some of the typical methods used to monitor hot carrier reliability in production and documents the specific event and symptoms caused by the failure of the implanter to properly sense wafer position. This intermittent failure resulted in transistors with an asymmetric source/drain profile. Standard measurements of Vt, Isub and other transistor parameters indicated normal performance for some layouts and severe hot carrier degradation and Vt shifts when measured in other orientations.","PeriodicalId":355898,"journal":{"name":"IEEE 1995 International Integrated Reliability Workshop. Final Report","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117061172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Fast detection of mobile ions for WLR monitoring WLR监测中移动离子的快速检测
IEEE 1995 International Integrated Reliability Workshop. Final Report Pub Date : 1995-10-22 DOI: 10.1109/IRWS.1995.493577
W. Xia, J. Scarpulla, M. Young, E. Sabin, L. Anderson
{"title":"Fast detection of mobile ions for WLR monitoring","authors":"W. Xia, J. Scarpulla, M. Young, E. Sabin, L. Anderson","doi":"10.1109/IRWS.1995.493577","DOIUrl":"https://doi.org/10.1109/IRWS.1995.493577","url":null,"abstract":"A new fast electrical technique for the detection of mobile ions in silicon processes using a simple field oxide test structure is presented. The method is ideal for WLR monitoring of mobile ions since its throughput is much higher than conventional slower methods such as the BTS (bias temperature sweep) method. The technique is based upon biasing a field oxide FET in a configuration resembling a source-follower, and observing the time varying output voltage. A simple model based upon ideal MOSFET characteristics is used to interpret the voltage waveforms produced by the new fast method. Data from about 30 wafer lots is presented, and a comparison made between the new method and a HTBS (high temperature bias sweep) measurement-a modified version of the BTS method. The correlation was found to be greatly improved by introducing a short bake to diffuse the mobile ions (suspected to be Na) into the region of the field oxide near the channel.","PeriodicalId":355898,"journal":{"name":"IEEE 1995 International Integrated Reliability Workshop. Final Report","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130245198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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