IEEE 1995 International Integrated Reliability Workshop. Final Report最新文献

Particulate contamination control in plasma processing: building-in reliability for semiconductor fabrication 等离子体加工中的微粒污染控制:半导体制造的内置可靠性

IEEE 1995 International Integrated Reliability Workshop. Final Report Pub Date : 1995-12-31 DOI: 10.1109/IRWS.1995.493585

G. Selwyn

{"title":"Particulate contamination control in plasma processing: building-in reliability for semiconductor fabrication","authors":"G. Selwyn","doi":"10.1109/IRWS.1995.493585","DOIUrl":"https://doi.org/10.1109/IRWS.1995.493585","url":null,"abstract":"Plasma processing is used for /spl sim/35% of the process steps required for semiconductor manufacturing. Recent studies have shown that plasma processes create the greatest amount of contaminant dust of all the manufacturing steps required for device fabrication. Often, the level of dust in a plasma process tool exceeds the cleanroom by several orders of magnitude. Particulate contamination generated in a plasma tool can result in reliability problems as well as device failure. Inter-level wiring shorts different levels of metallization on a device is a common result of plasma particulate contamination. We have conducted a thorough study of the physics and chemistry involved in particulate formation and transport in plasma tools. In-situ laser light scattering (LLS) is used for real-time detection of the contaminant dust. The results of this work are highly surprising: all plasmas create dust; the dust can be formed by homogeneous as well as heterogeneous chemistry; this dust is charged and suspended in the plasma; additionally, it is transported to favored regions of the plasma, such as those regions immediately above wafers. Fortunately, this work has also led to a novel means of controlling and eliminating these unwanted contaminants: electrostatic \"drainpipes\" engineered into the electrode by means of specially designed grooves. These channel the suspended particles out of the plasma and into the pump port before they can fall onto the wafer.","PeriodicalId":355898,"journal":{"name":"IEEE 1995 International Integrated Reliability Workshop. Final Report","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114347930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

A new approach for predicting AC hot carrier lifetime 预测交流热载流子寿命的新方法

IEEE 1995 International Integrated Reliability Workshop. Final Report Pub Date : 1995-10-22 DOI: 10.1109/IRWS.1995.493586

H. Kato

引用次数: 0

A case study in a 100/spl times/reduction in sodium ions in a 0.8 /spl mu/m BiCMOS process using triangular voltage sweep 在0.8 /spl mu/m的BiCMOS工艺中，使用三角电压扫描使钠离子减少100/spl倍的案例研究

IEEE 1995 International Integrated Reliability Workshop. Final Report Pub Date : 1995-10-22 DOI: 10.1109/IRWS.1995.493574

L. Anderson, S. Parikh, S. Nagalingam, C. Haidinyak

引用次数: 4

A design reliability methodology for CMOS VLSI circuits CMOS VLSI电路的设计可靠性方法

IEEE 1995 International Integrated Reliability Workshop. Final Report Pub Date : 1995-10-22 DOI: 10.1109/IRWS.1995.493572

L. Oshiro, R. Radojcic

引用次数: 4

WLR fast tests for characterization of a BiCMOS process and identification of mobile ionic contamination 用于BiCMOS过程表征和移动离子污染识别的WLR快速测试

IEEE 1995 International Integrated Reliability Workshop. Final Report Pub Date : 1995-10-22 DOI: 10.1109/IRWS.1995.493601

M. Poulter, D. Brisbin

引用次数: 1

A study of EEPROM endurance correlation with wafer level reliability data EEPROM寿命与晶片级可靠性数据的相关性研究

IEEE 1995 International Integrated Reliability Workshop. Final Report Pub Date : 1995-10-22 DOI: 10.1109/IRWS.1995.493576

D. Wilkie, M. Hensen

引用次数: 1

Building reliability into an EPROM cell using in-line WLR monitors 使用在线WLR监视器构建可靠性到EPROM单元

IEEE 1995 International Integrated Reliability Workshop. Final Report Pub Date : 1995-10-22 DOI: 10.1109/IRWS.1995.493573

G. Madson, D. Probst, L. Rawlins

{"title":"Building reliability into an EPROM cell using in-line WLR monitors","authors":"G. Madson, D. Probst, L. Rawlins","doi":"10.1109/IRWS.1995.493573","DOIUrl":"https://doi.org/10.1109/IRWS.1995.493573","url":null,"abstract":"A systematic deprogramming failure on a small percentage of the wafers produced on our 0.8 micron EPROM line threatened profitability and reliability. The development of an in-line JEDEC Qbd test on scribe line capacitors lead to the finding of a direct correlation of the inter-poly oxide voltage at breakdown (Vbd) to deprogramming. Using the inline Vbd correlation enabled the discovery of the root cause of deprogramming-asperities growing from the first poly side wall creating a local area of a enhanced field allowing tunneling of electrons from the floating gates during write cycles of adjacent bits. Because the asperities were not created by one source, but from multiple sources, finding the root cause proved to be a formidable task. Before using the in-line Vbd test, wafer sort provided the only feedback. By using the in-line monitor, the evaluation time was reduced by 70%, reducing the time in our cycles of learning. With the reduced cycle time, a systematic approach to finding the root causes became possible. Screening experiments eliminated as many variables as possible. Finally, the contributing process steps were identified and further experiments lead to the development of a robust process. Descriptions of the methods followed and the resulting process changes are discussed.","PeriodicalId":355898,"journal":{"name":"IEEE 1995 International Integrated Reliability Workshop. Final Report","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130391280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Passivation scheme impact on retention reliability of non volatile memory cells 钝化方案对非易失性存储单元保持可靠性的影响

IEEE 1995 International Integrated Reliability Workshop. Final Report Pub Date : 1995-10-22 DOI: 10.1109/IRWS.1995.493569

R. Bottini, A. Cascella, F. Pio, B. Vajana

{"title":"Passivation scheme impact on retention reliability of non volatile memory cells","authors":"R. Bottini, A. Cascella, F. Pio, B. Vajana","doi":"10.1109/IRWS.1995.493569","DOIUrl":"https://doi.org/10.1109/IRWS.1995.493569","url":null,"abstract":"Non Volatile Memory cells must retain the data (i.e. the charge stored in the floating gate) during the device lifetime, typically at least 10 years. In this work we study the impact of different passivation layers on the data retention of single polysilicon EEPROM cells, processed with an advanced 0.7 /spl mu/m process technology. Three passivation layers have been considered: (1) Phosphorus doped Silicon Glass (PSG), (2) Planarized (Oxynitride/SOG/Oxynitride/PSG), and (3) UV-Nitride. Accelerated tests were performed at high temperature (250-350/spl deg/C) up to 500 hours in order to monitor the threshold voltage shift of the floating gate transistor programmed either in the written or in the erased state. In the case of planarized passivation and of UV-nitride passivation the charge loss is small and it largely fulfils the data retention requirements; in the case of PSG passivation a much higher charge loss is observed. The effect of tunnel oxide degradation after extended cycling (1 Mcycles) has been investigated. No significant difference has been found after 200 hours at 250/spl deg/C between cycled and one time programmed cells, evidencing that the charge loss mechanism does not involve tunnel oxide degradation. The activation energy of the charge loss mechanism has been evaluated in the case of planarized passivation, using written cells. The measured value is 1.84 eV. The impact of different passivation schemes was studied with conventional techniques, the best results were obtained with the planarized passivation stack and with the UV-nitride layer.","PeriodicalId":355898,"journal":{"name":"IEEE 1995 International Integrated Reliability Workshop. Final Report","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122022726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Corner point lot qualification technique 角点批号鉴定技术

IEEE 1995 International Integrated Reliability Workshop. Final Report Pub Date : 1995-10-22 DOI: 10.1109/IRWS.1995.493571

J. Gagnon, D. Potts, S.C. Park, R. Whitcomb

引用次数: 2

A new method to statistically monitor active area spread and oxide thinning in real devices 一种在实际器件中统计监测有源面积扩展和氧化物减薄的新方法

IEEE 1995 International Integrated Reliability Workshop. Final Report Pub Date : 1995-10-22 DOI: 10.1109/IRWS.1995.493588

G. Ghidini, C. Clementi

引用次数: 1