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IEEE 1995 International Integrated Reliability Workshop. Final Report最新文献

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Reduced oxide reliability due to multilevel metalization process 多层金属化工艺导致氧化物可靠性降低
IEEE 1995 International Integrated Reliability Workshop. Final Report Pub Date : 1995-10-22 DOI: 10.1109/IRWS.1995.493582
K. Noguchi, T. Horiuchi
{"title":"Reduced oxide reliability due to multilevel metalization process","authors":"K. Noguchi, T. Horiuchi","doi":"10.1109/IRWS.1995.493582","DOIUrl":"https://doi.org/10.1109/IRWS.1995.493582","url":null,"abstract":"The effect of multilevel metalization process on oxide reliability was investigated. In addition to the well-known charging damage from plasma etching, other types of damages were identified. They are non-electrical damage due to ILD process, and charging damage due to plasma oxide deposition. Recovery effects of plasma induced charging damage were also observed. Since the damage responds differently to measurement depending on the stress bias condition, an appropriate choice of stress condition is important to identify the nature of the damage.","PeriodicalId":355898,"journal":{"name":"IEEE 1995 International Integrated Reliability Workshop. Final Report","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129362490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Fast test at wafer-level for endurance of tunnel oxide 在晶圆级快速测试隧道氧化物的耐久性
IEEE 1995 International Integrated Reliability Workshop. Final Report Pub Date : 1995-10-22 DOI: 10.1109/IRWS.1995.493587
Sik-Han Sob, C. Messick, Chih-Chang Chen, Chuanzhen Liu, B. Bakel, R. Peterson, L. Sadwick
{"title":"Fast test at wafer-level for endurance of tunnel oxide","authors":"Sik-Han Sob, C. Messick, Chih-Chang Chen, Chuanzhen Liu, B. Bakel, R. Peterson, L. Sadwick","doi":"10.1109/IRWS.1995.493587","DOIUrl":"https://doi.org/10.1109/IRWS.1995.493587","url":null,"abstract":"The standard method for characterizing the quality of thin oxide is to use charge to breakdown (QBD) either by JRAMP or VRAMP. In devices such as FLASH and EEPROM where bidirectional current injection through the thin tunneling oxide is a normal mode of operation, QBD does not correlate well with endurance. This study looks at the temperature and electric field dependency of the endurance of thin tunnel oxide. Data show that the thermal effect of endurance can be modeled by the Arrhenius function and it also has an exponential 1/E dependence. Temperature and electric field can be used as accelerating factors for designing a fast test for endurance. The test time for the endurance can be cut down to less than 10 s by adjusting either of these accelerating factors. A proposal for implementing a fast test at wafer level for endurance of the thin tunnel oxide is given.","PeriodicalId":355898,"journal":{"name":"IEEE 1995 International Integrated Reliability Workshop. Final Report","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121563402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Building in reliability (BIR) with critical nodes 关键节点内建可靠性(BIR)
IEEE 1995 International Integrated Reliability Workshop. Final Report Pub Date : 1995-10-22 DOI: 10.1109/IRWS.1995.493599
M. Dion
{"title":"Building in reliability (BIR) with critical nodes","authors":"M. Dion","doi":"10.1109/IRWS.1995.493599","DOIUrl":"https://doi.org/10.1109/IRWS.1995.493599","url":null,"abstract":"Advances in technology have enabled the semiconductor industry to reduce reliability failure rates. However, the cost to continue the past methods of understanding reliability performance of these advanced technologies is increasing rapidly. While it is increasingly difficult to measure the reducing reliability failure rates, the philosophy of continuous improvement can be applied to the determination of reliability by focusing on the various steps in the manufacturing systems used to build the products. Building-in-reliability (BIR) is a philosophy where the inputs to manufacturing process steps affecting reliability are identified, controlled and improved leading to continuous improvement in product reliability. With BIR significant effort is placed on identification of the process steps, or process nodes, that have a significant effect on reliability.","PeriodicalId":355898,"journal":{"name":"IEEE 1995 International Integrated Reliability Workshop. Final Report","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134593412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Dielectric step stress and life stress comparison 介电阶跃应力与寿命应力比较
IEEE 1995 International Integrated Reliability Workshop. Final Report Pub Date : 1995-10-22 DOI: 10.1109/IRWS.1995.493602
A. Strong, E. Wu, R. Bolam
{"title":"Dielectric step stress and life stress comparison","authors":"A. Strong, E. Wu, R. Bolam","doi":"10.1109/IRWS.1995.493602","DOIUrl":"https://doi.org/10.1109/IRWS.1995.493602","url":null,"abstract":"Voltage life-stress results have been compared with voltage step stress results. The figure of merit chosen for this comparison was TDDB. Two different oxides were used, one having a thickness of 13.5 nm and the other having a thickness of 8.2 nm.","PeriodicalId":355898,"journal":{"name":"IEEE 1995 International Integrated Reliability Workshop. Final Report","volume":"144 9-10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129472691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
F contamination effects on intrinsic and extrinsic gate oxide reliability 污染对内在和外在栅极氧化物可靠性的影响
IEEE 1995 International Integrated Reliability Workshop. Final Report Pub Date : 1995-10-22 DOI: 10.1109/IRWS.1995.493581
G. Ghidini, D. Drera, F. Maugain
{"title":"F contamination effects on intrinsic and extrinsic gate oxide reliability","authors":"G. Ghidini, D. Drera, F. Maugain","doi":"10.1109/IRWS.1995.493581","DOIUrl":"https://doi.org/10.1109/IRWS.1995.493581","url":null,"abstract":"The subject of this work is the study of the effect of fluorine contaminants on the intrinsic and extrinsic gate oxide reliability. After a brief introduction in which the author explains the known effects of fluorine contaminants on the oxide quality, the the test structures used in this work to separate the effect of fluorine contaminants are described. The author then presents some typical TDDB distributions showing the effects of fluorine contaminants and reports also a study of the TDDB dependence on the tested areas to verify if clustering of defects are present at such high fluorine concentrations. The author explains how he statistically treated the experimental results. He considered bimodal distributions separated in an intrinsic and an extrinsic part, showing in detail the effects of fluorine on the intrinsic and extrinsic failure mode. The author also presents some data on charge trapping to explain the above results and finally draws some conclusions.","PeriodicalId":355898,"journal":{"name":"IEEE 1995 International Integrated Reliability Workshop. Final Report","volume":"17 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128632794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Assessment of a unipolar pulsed ramp for the characterisation of MOS gate oxide reliability 单极脉冲斜坡对MOS栅氧化物可靠性表征的评估
IEEE 1995 International Integrated Reliability Workshop. Final Report Pub Date : 1995-10-22 DOI: 10.1109/IRWS.1995.493595
A. Martin, P. O'Sullivan, A. Mathewson
{"title":"Assessment of a unipolar pulsed ramp for the characterisation of MOS gate oxide reliability","authors":"A. Martin, P. O'Sullivan, A. Mathewson","doi":"10.1109/IRWS.1995.493595","DOIUrl":"https://doi.org/10.1109/IRWS.1995.493595","url":null,"abstract":"The unipolar pulsed ramp is compared to the commonly used staircase ramp. RVS and combined RVS/CVS measurements are performed on MOS gate oxides using both types of ramps with a wide range of ramp parameters. From the experiments it can be concluded that the unipolar pulsed ramp shows identical measurement results to the staircase ramp.","PeriodicalId":355898,"journal":{"name":"IEEE 1995 International Integrated Reliability Workshop. Final Report","volume":"244 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116145772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Time-dependent dielectric breakdown of intrinsic SiO/sub 2/ films under dynamic stress 动态应力作用下本征SiO/ sub2 /薄膜的介电击穿
IEEE 1995 International Integrated Reliability Workshop. Final Report Pub Date : 1995-10-22 DOI: 10.1109/IRWS.1995.493583
P. Chaparala, J. Suehle, C. Messick, M. Roush
{"title":"Time-dependent dielectric breakdown of intrinsic SiO/sub 2/ films under dynamic stress","authors":"P. Chaparala, J. Suehle, C. Messick, M. Roush","doi":"10.1109/IRWS.1995.493583","DOIUrl":"https://doi.org/10.1109/IRWS.1995.493583","url":null,"abstract":"We present time-dependent dielectric breakdown (TDDB) characteristics for 9, 15, and 22 nm silicon dioxide films stressed under DC, unipolar, and bipolar pulsed bias conditions. Our results indicate that the increased lifetime observed under pulsed stress conditions diminishes as the stress electric field and oxide thickness are reduced. TDDB data under pulse bias conditions exhibit similar field and temperature dependencies as under static stress. C-V measurements indicate that lifetime enhancement only occurs for electric fields and thickness where charge trapping is significant.","PeriodicalId":355898,"journal":{"name":"IEEE 1995 International Integrated Reliability Workshop. Final Report","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130299267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Using CHARM-2 wafers to increase reliability in ion implant processing 采用CHARM-2晶圆提高离子植入加工的可靠性
IEEE 1995 International Integrated Reliability Workshop. Final Report Pub Date : 1995-10-22 DOI: 10.1109/IRWS.1995.493568
R. Bammi, S. Reno
{"title":"Using CHARM-2 wafers to increase reliability in ion implant processing","authors":"R. Bammi, S. Reno","doi":"10.1109/IRWS.1995.493568","DOIUrl":"https://doi.org/10.1109/IRWS.1995.493568","url":null,"abstract":"This paper describes the use of CHARM-2 charge monitor wafers as a BIR (building-in-reliability) tool to identify, monitor and ultimately reduce implanter charging levels, resulting in increased die yields and enhanced product and equipment reliability. An ion implant engineering group at National Semiconductor Corporation has actively used CHARM-2 wafers to quantify charge potential levels existing in high current ion implanters, to baseline and monitor their set of four high current implanters, and to correlate die-level charging patterns on CHARM-2 wafers to product wafer yield patterns. CHARM-2 wafers have been successfully used to determine the effects of implanter equipment modifications and process changes on wafer charging. These equipment modifications have resulted in reduced wafer charging levels, and have therefore, helped to resolve charging-related product yield and reliability issues. The equipment and process modifications implemented with the aid of CHARM-2 wafers have also resulted in significantly improved equipment reliability and increased process robustness. Because of the consistently high degree of correlation of CHARM-2 charging patterns to product wafer yield patterns, CHARM-2 wafers serve as an effective in-line, implant charge monitor in a manufacturing environment.","PeriodicalId":355898,"journal":{"name":"IEEE 1995 International Integrated Reliability Workshop. Final Report","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131323612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Assessing MOS gate oxide reliability on wafer level with ramped/constant voltage and current stress 在斜坡/恒定电压和电流应力下评估晶圆级MOS栅氧化物可靠性
IEEE 1995 International Integrated Reliability Workshop. Final Report Pub Date : 1995-10-22 DOI: 10.1109/IRWS.1995.493580
A. Martin, J. Suehle, P. Chaparala, P. O'Sullivan, A. Mathewson, C. Messick
{"title":"Assessing MOS gate oxide reliability on wafer level with ramped/constant voltage and current stress","authors":"A. Martin, J. Suehle, P. Chaparala, P. O'Sullivan, A. Mathewson, C. Messick","doi":"10.1109/IRWS.1995.493580","DOIUrl":"https://doi.org/10.1109/IRWS.1995.493580","url":null,"abstract":"In this study time to breakdown distributions are compared for MOS gate oxides which were stressed with a constant voltage (or current) stress or a pre-stressing voltage (or current) ramp followed by a constant voltage (or current) stress. Results show clearly that a pre-stress can increase time to breakdown. This increase is discussed and it is shown that it is dependent on oxide thickness, pre-stressing ramp rate and the processing conditions. The current-time (or voltage-time) characteristics of the constant stress are investigated and it is observed that charge trapping in the oxide is the reason for the time to breakdown increase. The pre-stressed oxide clearly shows a different initial charge trapping characteristic than the non prestressed oxide. The measurement results are discussed and it is demonstrated that the common understanding of oxide breakdown cannot explain the observed results. Therefore, a new parameter is proposed which is related to oxide degradation and breakdown and which has to be considered in combined ramped/constant stress measurements.","PeriodicalId":355898,"journal":{"name":"IEEE 1995 International Integrated Reliability Workshop. Final Report","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124815340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Migrated copper resistive shorts in plastic encapsulated devices 塑料封装装置中迁移的铜电阻短路
IEEE 1995 International Integrated Reliability Workshop. Final Report Pub Date : 1995-10-22 DOI: 10.1109/IRWS.1995.493603
P. Yalamanchili, A. Christou
{"title":"Migrated copper resistive shorts in plastic encapsulated devices","authors":"P. Yalamanchili, A. Christou","doi":"10.1109/IRWS.1995.493603","DOIUrl":"https://doi.org/10.1109/IRWS.1995.493603","url":null,"abstract":"Summary form only given. Integrated-circuit devices using the Al-Cu bond pad systems may be subjected to failure mechanisms based on electrolytic corrosion. The migratory copper resistive short (MCRS) failure mode is one example of this mechanism and results in the formation of filamentary or dendritic deposits of copper between adjacent bond pads on the IC chip. Such a failure mode was identified in the plastic encapsulated ECL devices. A number of advanced analytical techniques have been applied in order to characterize the failure mechanism. These techniques included environmental scanning electron microscopy (ESEM), energy dispersive X-ray spectroscopy (EDX) and c-mode scanning acoustic microscopy (C-SAM). A model, based on the physics of condensation, ionic migration and thermally activated mechanism, was developed, and verified with the field returned failure data. The source of moisture, copper and ionic contaminants that accelerate the failure mechanism were also discussed.","PeriodicalId":355898,"journal":{"name":"IEEE 1995 International Integrated Reliability Workshop. Final Report","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116188821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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