Wafer level reliability procedures to monitor gate oxide quality using V ramp and J ramp test methodology

Abstract

Comparison between voltage ramp and current ramp test methods in detecting low level oxide defects is presented. Besides test conditions, such as voltage or current ramp rate, initial stress voltage or current density, gate oxide area, which are already known to be determining factors, several other factors are shown in this paper to impact defect density as measured by J ramp and V ramp test methods. These factors are: gate oxide thickness, test structure layout, types of test structures, and wafer processing.