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Proceedings. 4th International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (Cat. No.98EX153)最新文献

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Enhancement of fast-flow underfill performance by use of silane additives 硅烷添加剂增强快流底填料性能
Proceedings. 4th International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (Cat. No.98EX153) Pub Date : 1998-03-15 DOI: 10.1109/ISAPM.1998.664427
M. Vincent, C. Wong
{"title":"Enhancement of fast-flow underfill performance by use of silane additives","authors":"M. Vincent, C. Wong","doi":"10.1109/ISAPM.1998.664427","DOIUrl":"https://doi.org/10.1109/ISAPM.1998.664427","url":null,"abstract":"A challenge in flip-chip technology development is to improve the thermo-mechanical reliability of the flip-chip assembly. To increase reliability, an underfill encapsulant is applied to the gap between die and substrate to provide thermal-mechanical protection as well as environmental protection to the assembly. The fast-flow method is currently the most widely used method for applying the underfill to the gap. This method dispenses the underfill along one or two sides of the die and allows the underfill to fill the gap by capillary flow. There are two major opportunities for improvement of the fast-flow method of underfilling: flow time and cure time. This paper presents work on enhancement of the underfill viscosity and wetting properties by silane coupling agents to decrease the time to underfill the die. Viscosity, contact angle measurements, and flow time in a simulated flip-chip are used to test the effects of the additives in the underfill.","PeriodicalId":354229,"journal":{"name":"Proceedings. 4th International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (Cat. No.98EX153)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133984925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Chip scale packaging and redistribution 芯片规模封装和再分配
Proceedings. 4th International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (Cat. No.98EX153) Pub Date : 1998-03-15 DOI: 10.1109/ISAPM.1998.664436
P. Magill, W. C. Machon, G. Rinne, J. D. Mis, J.W. Baggs
{"title":"Chip scale packaging and redistribution","authors":"P. Magill, W. C. Machon, G. Rinne, J. D. Mis, J.W. Baggs","doi":"10.1109/ISAPM.1998.664436","DOIUrl":"https://doi.org/10.1109/ISAPM.1998.664436","url":null,"abstract":"Packaging of electronic components is in a transitional phase due to the relentless progress of transistor integration that is going on in the semiconductor environment. While all manufacturers may want to transition directly to flip chip, for a number of reasons, that may not always be possible. There are areas, in electronic manufacturing, that are under pressure to increase packaging density and reduce size and weight. For these products, solutions that allow manufacturers to operate in an environment that is familiar while additional infrastructure for full flip chip is being implemented are valuable. Packaging solutions of this type are referred to as chip scale packages. The use of redistributed lines in the solder provides for the smallest possible chip scale package. This particular methodology for producing a chip scale package meets all of the criteria established for evaluating the worthiness of a CSP and can be manufactured today at the lowest possible cost.","PeriodicalId":354229,"journal":{"name":"Proceedings. 4th International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (Cat. No.98EX153)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132224140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Advances in ceramic packaging for power amplifiers 功率放大器陶瓷封装的研究进展
Proceedings. 4th International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (Cat. No.98EX153) Pub Date : 1998-03-15 DOI: 10.1109/ISAPM.1998.664471
R.E. Sigliano, F.J. Gaughan
{"title":"Advances in ceramic packaging for power amplifiers","authors":"R.E. Sigliano, F.J. Gaughan","doi":"10.1109/ISAPM.1998.664471","DOIUrl":"https://doi.org/10.1109/ISAPM.1998.664471","url":null,"abstract":"Power Amplifiers (PAs) for the past few years have been going through a drastic evolution in terms of packaging size and materials. Recent trends have seen the conversion from plastic molding packaging concepts of sizes from .5 to 1.0 CC to functional ceramic substrates incorporating matching circuits miniaturized to sizes of less than .02 CCs. In this paper PA packaging made of multilayer glass-ceramic materials incorporating matching circuits was manufactured. By utilizing a multilayer three-dimensional inductor filter design, a PA matching circuit with excellent electrical characteristics was produced.","PeriodicalId":354229,"journal":{"name":"Proceedings. 4th International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (Cat. No.98EX153)","volume":"55 7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123294381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Modeling the die attach adhesives process 模具黏合剂的建模过程
Proceedings. 4th International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (Cat. No.98EX153) Pub Date : 1998-03-15 DOI: 10.1109/ISAPM.1998.664455
J. Taweeplengsangsuke, J. Hsiung, R. Pearson
{"title":"Modeling the die attach adhesives process","authors":"J. Taweeplengsangsuke, J. Hsiung, R. Pearson","doi":"10.1109/ISAPM.1998.664455","DOIUrl":"https://doi.org/10.1109/ISAPM.1998.664455","url":null,"abstract":"Multi-step curing was performed to reduce the residual cure stress in the polymeric adhesives. The longer the period of time at the lower temperature step of the 2-step curing gave the lower cure stress. In addition, the stress during the cool down process was investigated. At the point of decreasing temperature, the stress dramatically increases. The higher temperature difference, the larger the residual stress.","PeriodicalId":354229,"journal":{"name":"Proceedings. 4th International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (Cat. No.98EX153)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121060634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Heat transfer modules for cooling electronics packages 用于冷却电子封装的传热模块
Proceedings. 4th International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (Cat. No.98EX153) Pub Date : 1998-03-15 DOI: 10.1109/ISAPM.1998.664461
W. Black, A. Giezer, J. Hartley
{"title":"Heat transfer modules for cooling electronics packages","authors":"W. Black, A. Giezer, J. Hartley","doi":"10.1109/ISAPM.1998.664461","DOIUrl":"https://doi.org/10.1109/ISAPM.1998.664461","url":null,"abstract":"The Thermal Management Group of the Packaging Research Center at the Georgia Institute of Technology is developing radically new and highly efficient cooling technologies suitable for on-the-spot and on-demand use on individual chips, MCMs and electronic packages. Our research efforts focus on the development of thermal management hardware that will target these heat flux levels in a low-profile, compact, reliable and inexpensive package. The cooling technologies are based manipulation of miniature single-phase jets using impulse actuators. The group is also developing two-phase versions for high heat flux applications. The technology can be applied as an open system (e.g. as a clip-on device for existing chips) or as a self-contained, integrated heat transfer module. The scalability, connectivity, and stackability of such modules could potentially provide significant improvements over current air-cooled thermal management schemes.","PeriodicalId":354229,"journal":{"name":"Proceedings. 4th International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (Cat. No.98EX153)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125555167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Packaging aspects of CVD diamond in high performance electronics requiring enhanced thermal management 封装方面的CVD金刚石在高性能电子需要加强热管理
Proceedings. 4th International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (Cat. No.98EX153) Pub Date : 1998-03-15 DOI: 10.1109/ISAPM.1998.664463
R. Petkie, P. Santini
{"title":"Packaging aspects of CVD diamond in high performance electronics requiring enhanced thermal management","authors":"R. Petkie, P. Santini","doi":"10.1109/ISAPM.1998.664463","DOIUrl":"https://doi.org/10.1109/ISAPM.1998.664463","url":null,"abstract":"The application of CVD diamond substrates has increased in recent years due to lower manufacturing costs of CVD diamond and an increased demand for high performance heat spreaders in thermal management. The materials and packaging aspects specific to diamond substrates and the most recent applications are discussed. Topics include thin and thick film metallization schemes, via filling, die attach, flange materials, brazing, and thermal performance. Materials processing, such as brazing and screen printing, are discussed in terms of compatibility and cost. Some metallization schemes to diamond, for example, have proven to be very robust in terms of temperature, time, and reducing gas ambient for lead attach, while screen printing reduces manufacturing costs. Optimization of die attach adhesion while minimizing thermal resistance is addressed and a comparison of BeO and CVD diamond packages in terms of thermal management is illustrated with temperature color maps.","PeriodicalId":354229,"journal":{"name":"Proceedings. 4th International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (Cat. No.98EX153)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132453466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Overview of advanced composites for thermal management 热管理先进复合材料概述
Proceedings. 4th International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (Cat. No.98EX153) Pub Date : 1998-03-15 DOI: 10.1109/ISAPM.1998.664458
C. Zweben
{"title":"Overview of advanced composites for thermal management","authors":"C. Zweben","doi":"10.1109/ISAPM.1998.664458","DOIUrl":"https://doi.org/10.1109/ISAPM.1998.664458","url":null,"abstract":"A variety of new, advanced composites are now available which provide great advantages over conventional materials for thermal control and electronic packaging. This brief paper provides an overview of advanced composites used in thermal management, including properties, applications and future trends. The focus is on materials that have thermal conductivities that are at least as high as those of aluminum alloys.","PeriodicalId":354229,"journal":{"name":"Proceedings. 4th International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (Cat. No.98EX153)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122369063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Microvia technology in MCM-D/L-need, challenge, and response MCM-D/ l中的微孔技术需求、挑战和响应
Proceedings. 4th International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (Cat. No.98EX153) Pub Date : 1998-03-15 DOI: 10.1109/ISAPM.1998.664434
Weiping Li, R. Tummala
{"title":"Microvia technology in MCM-D/L-need, challenge, and response","authors":"Weiping Li, R. Tummala","doi":"10.1109/ISAPM.1998.664434","DOIUrl":"https://doi.org/10.1109/ISAPM.1998.664434","url":null,"abstract":"This paper discusses the performance and cost needs of high-density wiring substrates and the challenges to the materials and processes of MCM-D/L technology. The approach proposed by the Packaging Research Center (PRC) at Georgia Tech to meet these needs and challenges is presented along with some up-to-date advances in microvia technology. Finally, further research and development planned on microvia technology is presented.","PeriodicalId":354229,"journal":{"name":"Proceedings. 4th International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (Cat. No.98EX153)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116889455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A prototype test system for massively-parallel electrical testing of high density interconnect substrates 一种用于高密度互连衬底大规模并联电性测试的原型测试系统
Proceedings. 4th International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (Cat. No.98EX153) Pub Date : 1998-03-15 DOI: 10.1109/ISAPM.1998.664450
K. Newman, D. Keezer
{"title":"A prototype test system for massively-parallel electrical testing of high density interconnect substrates","authors":"K. Newman, D. Keezer","doi":"10.1109/ISAPM.1998.664450","DOIUrl":"https://doi.org/10.1109/ISAPM.1998.664450","url":null,"abstract":"Summary form only given. Conventional tests for electrical interconnections in high density substrates utilize one or more moving probes to measure net capacitance and/or resistance between nodes. These methods provide adequate fault coverage for \"opens\" and \"shorts\". However, large area substrates containing thousands of nets require excessive time for mechanical positioning of the probe(s). The researchers propose an alternative method whereby all exposed nodes sue simultaneously connected to a high channel count test system. The network is then electrically tested in a single step. During the test, each net is excited through one node with a unique digital \"signature\" made up of 16 to 32 serial bits. Other nodes connected to these nets are monitored by the test system. All monitored signatures should match with the expected signatures in a fault-free substrate. A faulty substrate will exhibit one or more incorrect signatures. A prototype test system that implements the digital test function is described in this work. The system is constructed using low-cost Field Programmable Gate Arrays (FPGAs), so that expansion to large channel count is economically feasible. Both an immediate Pass/Fail response and diagnostic information is obtained in a fraction of a second. The diagnostic data may optionally be analyzed if fault classification is desired.","PeriodicalId":354229,"journal":{"name":"Proceedings. 4th International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (Cat. No.98EX153)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121974744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Advanced microelectronic packaging using BeO ceramics 采用BeO陶瓷的先进微电子封装
Proceedings. 4th International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (Cat. No.98EX153) Pub Date : 1998-03-15 DOI: 10.1109/ISAPM.1998.664472
J. L. Sepulveda
{"title":"Advanced microelectronic packaging using BeO ceramics","authors":"J. L. Sepulveda","doi":"10.1109/ISAPM.1998.664472","DOIUrl":"https://doi.org/10.1109/ISAPM.1998.664472","url":null,"abstract":"Beryllia ceramics have been successfully used during the last forty years to produce reliable packaging solutions for a wide range of commercial microelectronic packaging applications. Ceramic properties have been well defined and consistently controlled throughout production of many millions of circuits to insure high performance operation and product reliability.","PeriodicalId":354229,"journal":{"name":"Proceedings. 4th International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (Cat. No.98EX153)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130630773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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