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Proceedings. 4th International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (Cat. No.98EX153)最新文献

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Soft error rates in solder bumped packaging 焊料碰撞封装中的软错误率
Proceedings. 4th International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (Cat. No.98EX153) Pub Date : 1998-03-15 DOI: 10.1109/ISAPM.1998.664444
M. W. Roberson
{"title":"Soft error rates in solder bumped packaging","authors":"M. W. Roberson","doi":"10.1109/ISAPM.1998.664444","DOIUrl":"https://doi.org/10.1109/ISAPM.1998.664444","url":null,"abstract":"Many of the heavier elements used in chip packaging undergo radioactive decay and emit energetic alpha particles. Although the rate of emission is extremely low in terms of health concerns, over the operational life of a circuit the probability of a radiation-induced soft error can be substantial. In this paper I review the physical basis of alpha particle emission and present measurements of the alpha particle emission from materials used in MCNC's solder bumping process, including PbSn solder and BCB.","PeriodicalId":354229,"journal":{"name":"Proceedings. 4th International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (Cat. No.98EX153)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114683547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Enhancement of underfill adhesion to die and substrate by use of silane additives 使用硅烷添加剂增强底填料对模具和基材的附着力
Proceedings. 4th International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (Cat. No.98EX153) Pub Date : 1998-03-15 DOI: 10.1109/ISAPM.1998.664432
M. Vincent, L. Meyers, C. Wong
{"title":"Enhancement of underfill adhesion to die and substrate by use of silane additives","authors":"M. Vincent, L. Meyers, C. Wong","doi":"10.1109/ISAPM.1998.664432","DOIUrl":"https://doi.org/10.1109/ISAPM.1998.664432","url":null,"abstract":"A challenge in flip-chip technology development is to improve the thermo-mechanical reliability of the flip-chip assembly. To increase reliability, an underfill encapsulant is applied to the gap between die and substrate to provide thermal-mechanical protection as well as environmental protection to the assembly. There are three main underfill material properties that contribute to thermo-mechanical reliability of the flip-chip assembly: 1) modulus, 2) coefficient of thermal expansion (CTE), and 3) adhesion. This paper deals with improving the adhesion of the underfill to die and substrate surfaces which could lead to improvements in thermo-mechanical reliability. Adhesion of the underfill to die and substrate surfaces can be enhanced by addition of silane coupling agents to the underfill. This paper presents results on shear strength as a measure of adhesion strength for underfill bonded to alumina and FR4 with solder mask.","PeriodicalId":354229,"journal":{"name":"Proceedings. 4th International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (Cat. No.98EX153)","volume":"128 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125777992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
A fundamental study on silver flakes for conductive adhesives 导电胶粘剂用银片的基础研究
Proceedings. 4th International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (Cat. No.98EX153) Pub Date : 1998-03-15 DOI: 10.1109/ISAPM.1998.664466
D. Lu, C. Wong, Q. Tong
{"title":"A fundamental study on silver flakes for conductive adhesives","authors":"D. Lu, C. Wong, Q. Tong","doi":"10.1109/ISAPM.1998.664466","DOIUrl":"https://doi.org/10.1109/ISAPM.1998.664466","url":null,"abstract":"Silver (Ag) flakes are widely used as fillers for electrically conductive adhesives (ECAs). The Ag flakes need to be pretreated with organic lubricants to ensure the proper rheology of the ECAs. Lubricants on the Ag flakes influence rheology, conductivity and other properties of ECAs. The surface composition of a Ag flake was investigated by X-ray photoelectron spectroscopy. The nature of the lubricant on a Ag flake and the interaction between the lubricant and Ag flake surface were studied by diffuse reflectance infrared spectroscopy. Thermal decomposition of the lubricant was also studied by differential scanning calorimetry. In addition, the effects of some chemical compounds on lubricant removal were also investigated.","PeriodicalId":354229,"journal":{"name":"Proceedings. 4th International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (Cat. No.98EX153)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132641900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 36
In situ elastic property characterization of flip-chip underfills 倒装充填体的原位弹性特性表征
Proceedings. 4th International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (Cat. No.98EX153) Pub Date : 1998-03-15 DOI: 10.1109/ISAPM.1998.664443
S. Canumalla, M.G. Oravecz
{"title":"In situ elastic property characterization of flip-chip underfills","authors":"S. Canumalla, M.G. Oravecz","doi":"10.1109/ISAPM.1998.664443","DOIUrl":"https://doi.org/10.1109/ISAPM.1998.664443","url":null,"abstract":"The elastic properties of processing related inhomogeneities, such as filler settling and voids, are characterized using the acoustic microscope. A procedure to calculate the acoustic impedance of materials, and hence the elastic properties, at internal interfaces is proposed. The acoustic impedance of the silica filled polymer material under the die is measured at different locations corresponding to areas of different brightness in the acoustic image. Correlating the acoustic impedance measurements with the HS-model indicated that a) darker areas are regions where the underfill has a homogeneous distribution of filler; b) lighter areas are regions characterized by filler settling. Destructive cross sectioning and microscopy confirmed the above predictions. Further, the elastic properties of the different areas adjacent to the die are estimated using the model. The relatively quick, nondestructive technique presented in this paper could be useful in advanced process control, rapid yield management and in providing input into package reliability studies (such as finite element analysis).","PeriodicalId":354229,"journal":{"name":"Proceedings. 4th International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (Cat. No.98EX153)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130932622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Economic and technical viability of integral passives 整体被动元件的经济和技术可行性
Proceedings. 4th International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (Cat. No.98EX153) Pub Date : 1998-03-15 DOI: 10.1109/ISAPM.1998.664470
J. Rector
{"title":"Economic and technical viability of integral passives","authors":"J. Rector","doi":"10.1109/ISAPM.1998.664470","DOIUrl":"https://doi.org/10.1109/ISAPM.1998.664470","url":null,"abstract":"Integral substrates (printed wiring boards with buried capacitors and/or resistors) can lower costs, improve component density, improve performance and reliability. Integral substrates are economically and technically viable for replacing a large portion of the ceramic chip capacitors used for decoupling and resistor chips and networks used for termination, pull-up and pull-down. However, passive integration is easier said than done. Integral substrates require new design and test systems, manufacturing processes and materials. Further investigation concludes that stable, low cost materials and processes, design and test systems are only half the equation. In order for this technology to reach its full market potential, time-to-market issues such as rapid prototyping and engineering changes must be solved.","PeriodicalId":354229,"journal":{"name":"Proceedings. 4th International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (Cat. No.98EX153)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114227580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
Creep behavior characterization of some new materials for high density interconnect substrates using dynamic mechanical analyzer (DMA) 基于动态力学分析仪(DMA)的新型高密度互连基板材料蠕变特性研究
Proceedings. 4th International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (Cat. No.98EX153) Pub Date : 1998-03-15 DOI: 10.1109/ISAPM.1998.664437
C. Wong, Y. Rao, J. Qu, S.X. Wu
{"title":"Creep behavior characterization of some new materials for high density interconnect substrates using dynamic mechanical analyzer (DMA)","authors":"C. Wong, Y. Rao, J. Qu, S.X. Wu","doi":"10.1109/ISAPM.1998.664437","DOIUrl":"https://doi.org/10.1109/ISAPM.1998.664437","url":null,"abstract":"Low-cost, high density interconnects (HDI) printed wiring board (PWB) is a critical technology for the next generation of high performance microelectronics. The precise characterization of the dielectr material used in the PWB and the solder mask, in particular, has significant effects on the HDI fabrication and reliability. For example, the design and reliability modeling of the HDI substrate depend crucially on the deformation rate and stress-strain relationship of these materials under specific thermal cyclic loading conditions. Dynamic mechanical analyzer (DMA) is a powerful instrument in measuring the viscoelasticity of materials in bending, compression, tension and shear. Using the TMA CONTROL FORCE testing mode of DMA, the creep behavior of some new dielectric and solder mask materials has been investigated and analyzed under different stress and temperature conditions. The results of this study provide critical parameters for the modeling of HDI substrate.","PeriodicalId":354229,"journal":{"name":"Proceedings. 4th International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (Cat. No.98EX153)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124680030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Sequential process modeling of SLIM substrate fabrication SLIM基板制造的顺序过程建模
Proceedings. 4th International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (Cat. No.98EX153) Pub Date : 1998-03-15 DOI: 10.1109/ISAPM.1998.664457
R. Dunne, S. Sitaraman
{"title":"Sequential process modeling of SLIM substrate fabrication","authors":"R. Dunne, S. Sitaraman","doi":"10.1109/ISAPM.1998.664457","DOIUrl":"https://doi.org/10.1109/ISAPM.1998.664457","url":null,"abstract":"A parametric process modeling approach has been implemented to simulate the sequential build-up process of a multilayered substrate. Generalized deformation models with element birth and death feature is used to activate and deactivate the material layers to simulate substrate fabrication. Using process models, one can determine the warpage and also axial and interfacial stresses at any intermediate stage in the process. This process-modeling approach is in contrast to the \"frozen-view\" models employed by many researchers, which are shown to yield overly conservative and sometimes erroneous results, leading to non-optimal design solutions. Residual warpage results are presented for the sequential build-up of a complex multilayered substrate with thin film passives integrated within the HDI (high density interconnect) layers. In addition, a comparison with the results using a frozen-view modeling approach is presented, and an alternate improved substrate processing technique is suggested to eliminate intermediate board warpage for a single-sided multilayer construction prior to polymer deposition.","PeriodicalId":354229,"journal":{"name":"Proceedings. 4th International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (Cat. No.98EX153)","volume":"35 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130469616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Combination of MCM-C technology with MCM-D technology using photosensitive polymers MCM-C技术与MCM-D技术结合使用光敏聚合物
Proceedings. 4th International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (Cat. No.98EX153) Pub Date : 1998-03-15 DOI: 10.1109/ISAPM.1998.664435
M. Topper, K. Scherpinski, R. Hahn, O. Ehrmann, H. Reichl, C. Schmaus, F. Bechtold
{"title":"Combination of MCM-C technology with MCM-D technology using photosensitive polymers","authors":"M. Topper, K. Scherpinski, R. Hahn, O. Ehrmann, H. Reichl, C. Schmaus, F. Bechtold","doi":"10.1109/ISAPM.1998.664435","DOIUrl":"https://doi.org/10.1109/ISAPM.1998.664435","url":null,"abstract":"A combination of ceramic substrate technology with thin film processes will be presented. Thick film hybrids are used for the bottom layers and a thin film metallization layer is deposited on top for the redistribution of the signal lines. For the evaluation of this combined technology test samples of multilayer ceramic substrates were manufactured. Polymer films having a low dielectric constants and thin film copper were used to fabricate the high density interconnection layer. Photosensitive polymers were selected to reduce the number of processing steps for via formation. Photo-BCB is recommended for the dielectric layers because planarization of the ceramic substrate is the most critical issue for the high density metallization. For thicker photo-BCB films a tank development process was installed at TUB/Fraunhofer-IZM which has the unique feature that the development time is nearly independent of the layer thickness. The reliability of the substrates was proofed by thermal cycling.","PeriodicalId":354229,"journal":{"name":"Proceedings. 4th International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (Cat. No.98EX153)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132570523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Solder alloy selection for flip chip on board 板上倒装芯片焊料合金的选择
Proceedings. 4th International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (Cat. No.98EX153) Pub Date : 1998-03-15 DOI: 10.1109/ISAPM.1998.664445
G. Rinne, J. D. Mis, P. Magill, W.C. Machon, J.W. Baggs
{"title":"Solder alloy selection for flip chip on board","authors":"G. Rinne, J. D. Mis, P. Magill, W.C. Machon, J.W. Baggs","doi":"10.1109/ISAPM.1998.664445","DOIUrl":"https://doi.org/10.1109/ISAPM.1998.664445","url":null,"abstract":"Improvements in PCB technology and the demand for smaller form factor at lower cost have provided the primary motivation for interest in flip chip on board (FCOB) assembly. With the development of direct chip attach (DCA) technology using high-lead solder bumps joined to eutectic solder on the board, these goals have been substantially met. However, efforts to further reduce overall product cost continue to motivate a search for a better solution. A survey of the literature and the user community was performed to assess the state of contemporary wisdom with regard to the selection of an appropriate solder alloy for FCOB applications. Although there is yet no consensus, the preliminary conclusion is that the current DCA technology (lead-rich bumps mounted by tin-rich solder to the PCB) is the most appropriate solution for the near term. Longer term, a homogenous system may offer simplified assembly with higher reliability at finer pitches. This would reduce cost by eliminating the solder deposition step for the PCB and, perhaps, eliminating the need for underfill.","PeriodicalId":354229,"journal":{"name":"Proceedings. 4th International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (Cat. No.98EX153)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129228329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Process induced warpage and residual stress in populated ball grid array substrate panel 填充球栅阵列衬底板的工艺致翘曲和残余应力
Proceedings. 4th International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (Cat. No.98EX153) Pub Date : 1998-03-15 DOI: 10.1109/ISAPM.1998.664452
S.X. Wu, Hua Lu, T. Yang, C. Yeh
{"title":"Process induced warpage and residual stress in populated ball grid array substrate panel","authors":"S.X. Wu, Hua Lu, T. Yang, C. Yeh","doi":"10.1109/ISAPM.1998.664452","DOIUrl":"https://doi.org/10.1109/ISAPM.1998.664452","url":null,"abstract":"In-process and pre-assembly warpage of printed wiring boards (PWBs) and packages can cause severe problems during component assembly. A numerical experimental hybrid approach is being developed to: (1) analyze the root cause of warpage and associated residual stresses of electronic packages such as ball grid array (EGA) and high density PWB; and, (2) reduce warpage. Advanced material characterization techniques have been applied to determine dimensional changes of a molding compound due to temperature and chemical reactions. Mechanical properties of the molding compound at various temperatures were also tested. The shadow moire interferometry technique is used to measure warpage of a BGA panel. A finite element analysis has also been conducted to investigate the warpage and residual stress evolution during the EGA assembly process. The study shows that the dimensional changes of the molding compound, due to both thermal expansion and chemical shrinkage, and the mismatch between the compound and silicon die/substrate can cause severe warpage.","PeriodicalId":354229,"journal":{"name":"Proceedings. 4th International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (Cat. No.98EX153)","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133735768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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