2005 International Symposium on Electronics Materials and Packaging最新文献_第4页

Studies on double-layered metal bumps for fine pitch flip chip applications 用于细间距倒装芯片的双层金属凸点研究

2005 International Symposium on Electronics Materials and Packaging Pub Date : 2005-12-11 DOI: 10.1109/EMAP.2005.1598242

H.-Y Son, Yong-Woon Yeo, Gi-Jo Jung, Jun-Kyu Lee, Joonyoung Choi, Chang-Joon Park, M. Suh, Soon-Jin Cho, K. Paik

{"title":"Studies on double-layered metal bumps for fine pitch flip chip applications","authors":"H.-Y Son, Yong-Woon Yeo, Gi-Jo Jung, Jun-Kyu Lee, Joonyoung Choi, Chang-Joon Park, M. Suh, Soon-Jin Cho, K. Paik","doi":"10.1109/EMAP.2005.1598242","DOIUrl":"https://doi.org/10.1109/EMAP.2005.1598242","url":null,"abstract":"In this paper, Cu/SnAg double-layered bumps structure was proposed and investigated for the fine pitch flip chip applications. Test chip was designed considering the recent high speed memory device and its pad size and pitch was 60/spl mu/m and 100/spl mu/m, respectively. Cu and SnAg bumps were fabricated as a 60/spl mu/m and 20/spl mu/m thickness on SiO/sub 2//Ti/TiN/Al/TiW/Cu on Si wafer using the electroplating method. Test chip was flip chip assembled with PCB substrates using thermo-compression bonding method. Because the pitch was very tight, the flip chip bonding of Cu/SnAg double bumps was very difficult and it affected several bonding parameters such as bonding pressure, temperature, time, Cu bump diameter and so on. The bonding results were evaluated through the cross-sectional image of interconnection and the electrical continuity test of daisy chain and bump resistance using 4-point Kelvin structure. The long time reliability tests like thermal cycling test and 85/spl deg/C/85% test are now in progress after flip chip bonding and underfill dispensing.","PeriodicalId":352550,"journal":{"name":"2005 International Symposium on Electronics Materials and Packaging","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126675378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A multifunctional test chip for microelectronic packaging and its application on RF property measurements 微电子封装多功能测试芯片及其在射频特性测量中的应用

2005 International Symposium on Electronics Materials and Packaging Pub Date : 2005-12-11 DOI: 10.1080/00207210701298305

K. Tseng, Yi-Hsun Hsion, B. Lwo, C. Kao

引用次数: 6

Hardness and elastic modulus of ZnO deposited materials by PLD method PLD法测定ZnO沉积材料的硬度和弹性模量

2005 International Symposium on Electronics Materials and Packaging Pub Date : 2005-12-11 DOI: 10.1109/EMAP.2005.1598255

Han-Ki Yoo, Yun-Sik Yu

{"title":"Hardness and elastic modulus of ZnO deposited materials by PLD method","authors":"Han-Ki Yoo, Yun-Sik Yu","doi":"10.1109/EMAP.2005.1598255","DOIUrl":"https://doi.org/10.1109/EMAP.2005.1598255","url":null,"abstract":"ZnO is an n-type semiconductor having a hexagonal wurzite structure. ZnO exhibits good piezoelectric, photoelectric and optical properties and might be a good candidate for an electroluminescence device like an UV laser diode. But the important problems, such as substrate kinds and substrate temperature are raised its head therefore need to optimize deposit condition. Also because these devices are very small and films are very thin, those are often prepared in limited quantities and shapes unsuitable for the extensive mechanical testing. In this present work, ZnO thin films are prepared on the glass, GaAs(100), Si(111) and Si(100) substrates at different temperatures by the pulsed laser deposition (PLD) method. ZnO was evaluated in term of crystalline through X-ray diffraction (XRD), mechanical properties such as hardness, elastic modulus through nanoindenter. XRD measurements indicate that the substrate temperature of 200-500, 200-500, 300-500, and 300-500/spl deg/C are the optimized conditions of crystalline for the glass, GaAs(100), Si(111), and Si(100) substrates, respectively. In spite of the films deposited on the different substrates, the films always show [002] orientation at the optimized conditions. Mechanical properties such as hardness and elastic modulus are influenced substrate crystallization. In case of Si(111) substrate, hardness and elastic modulus are about 10, 150GPa, respectively.","PeriodicalId":352550,"journal":{"name":"2005 International Symposium on Electronics Materials and Packaging","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114297076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Nonlinear dynamic behavior of thin PCB board for solder joint reliability study under shock loading 冲击载荷下薄PCB板焊接可靠性非线性动态行为研究

2005 International Symposium on Electronics Materials and Packaging Pub Date : 2005-12-11 DOI: 10.1109/EMAP.2005.1598274

L. W. Keat, Lee Yung Hsiang, Ajay Munigayah, Taylor We

{"title":"Nonlinear dynamic behavior of thin PCB board for solder joint reliability study under shock loading","authors":"L. W. Keat, Lee Yung Hsiang, Ajay Munigayah, Taylor We","doi":"10.1109/EMAP.2005.1598274","DOIUrl":"https://doi.org/10.1109/EMAP.2005.1598274","url":null,"abstract":"Solder joint reliability under shock loading condition has been a concern over the years especially with constant reductions in the characteristic dimensions of the package and the solder joint. With the impeding transition to lead free solder, attention has moved from temperature cycle failure to mechanical shock failure. A method has been developed that employs a specially designed shock test board (STB) to characterize the solder joint performance as a function of board surface strain. This unique test board can be adapted to a wide range of test and boundary conditions. Using this board, a range of shock inputs is tested to establish correlation of the dynamic response and solder joint damage severity. This method can be used to characterize solder joint performance at the component level, early in development. One can also provide board strain based design limits guide system design and prevent late discovery of solder joint issues. Modal analysis based and explicit time integration finite element models have been used to supplement understanding of the board response after shock loading. The shock model demonstrates good correlation of the strain on the thick board while thin board shows challenges in modeling prediction where nonlinear behavior observed. The modeling data also suggested that the maximum principal stress at the solder joint interface is a good failure criterion as it maps well with the actual failure region found.","PeriodicalId":352550,"journal":{"name":"2005 International Symposium on Electronics Materials and Packaging","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127235049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Evaluation of drop impact load for portable electronic components 便携式电子元件跌落冲击载荷的评定

2005 International Symposium on Electronics Materials and Packaging Pub Date : 2005-12-11 DOI: 10.1109/EMAP.2005.1598273

T. Omori, H. Inoue, N. Kawamura, M. Mukai, K. Kishimoto, T. Kawakami

引用次数: 1

A study in establishing flip-chip ball grid array (FCBGA) second level interconnect (SLI) reliability requirement by CFD simulation 通过CFD仿真研究了建立倒装球栅阵列(FCBGA)二级互连(SLI)可靠性要求

2005 International Symposium on Electronics Materials and Packaging Pub Date : 2005-12-11 DOI: 10.1109/EMAP.2005.1598278

L. Kwong, Tan Wooi Aun

引用次数: 2

Effects of the functional groups of nonconductive films (NCFs) on materials properties and reliability of NCF flip-chip-on-organic boards 非导电薄膜的官能团对非导电薄膜材料性能和可靠性的影响

2005 International Symposium on Electronics Materials and Packaging Pub Date : 2005-12-11 DOI: 10.1109/EMAP.2005.1598253

C. Chung, W. Kwon, Jin-Hyoung Park, Soon-Bok Lee, K. Paik

{"title":"Effects of the functional groups of nonconductive films (NCFs) on materials properties and reliability of NCF flip-chip-on-organic boards","authors":"C. Chung, W. Kwon, Jin-Hyoung Park, Soon-Bok Lee, K. Paik","doi":"10.1109/EMAP.2005.1598253","DOIUrl":"https://doi.org/10.1109/EMAP.2005.1598253","url":null,"abstract":"Nonconductive films (NCFs) are one of the conducting polymer adhesives alternatives for flip-chip interconnection. NCFs containing no conductive particles have functions of adhesion, insulation, and encapsulation. The most important issue in NCFs-bonded flip-chip-on-board (FCOB) assemblies is thermal cycling reliability. Thermo-mechanical properties such as glass transition temperature (Tg), modulus (E), and thermal expansion coefficient (CTE) of cured NCFs significantly affect to the thermal cycling reliability of NCFs bonded FCOB assembly. In this paper, we have mainly focused on the improvement of thermo-mechanical properties of NCFs by controlling the number of functional groups of NCFs resin. The functionality modified NCFs-bonded FCOB assembly showed significantly enhanced reliability under thermal cycling test environment (-40 /spl deg/C /spl sim/ 150 /spl deg/C, 1000 cycles). To compare the reliability of conventional and modified NCFs-bonded FCOB assemblies after thermal cycling test electrical analysis and scanning acoustic microscopy (SAM) investigation were performed. Thermal deformations of each NCFs-bonded FCOB assembly under thermal cycling environment were also investigated and quantitatively compared using high sensitivity Twyman-Green interferometry. According to experimental results, the functional groups of NCFs have great effects on thermomechanical properties of cured NCFs, the thermal deformation, and thermal cycling reliability of NCFs-bonded FCOB assemblies.","PeriodicalId":352550,"journal":{"name":"2005 International Symposium on Electronics Materials and Packaging","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131773240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Fatigue crack propagation analysis for microsolder joints with void 含孔洞微焊点疲劳裂纹扩展分析

2005 International Symposium on Electronics Materials and Packaging Pub Date : 2005-12-11 DOI: 10.1109/EMAP.2005.1598232

T. Terasaki, H. Tanie

引用次数: 5

Warpages of ACF-bonded COG packages induced from manufacturing and thermal cycling acf键合COG封装的翘曲由制造和热循环引起

2005 International Symposium on Electronics Materials and Packaging Pub Date : 2005-12-11 DOI: 10.1109/EMAP.2005.1598251

M. Tsai, C. Huang, C. Chiang, W. Chen, S. Yang

引用次数: 0

Local thermal deformation and residual stress of a thin Si chip mounted on a substrate using an area-arrayed flip chip structure 采用面阵倒装晶片结构，安装在基板上的薄硅晶片的局部热变形和残余应力

2005 International Symposium on Electronics Materials and Packaging Pub Date : 2005-12-11 DOI: 10.1109/EMAP.2005.1598265

H. Miura, N. Ueta, Y. Sato

引用次数: 13