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Evaluation of electromigration and stressmigration reliabilities of copper interconnects by a simple pulsed-current stressing technique 用简单脉冲电流应力技术评价铜互连的电迁移和应力迁移可靠性
Proceedings of IEEE International Electron Devices Meeting Pub Date : 1993-12-05 DOI: 10.1109/IEDM.1993.347354
H. Yamada, T. Hoshi, T. Takewaki, T. Shibata, T. Ohmi, T. Nitta
{"title":"Evaluation of electromigration and stressmigration reliabilities of copper interconnects by a simple pulsed-current stressing technique","authors":"H. Yamada, T. Hoshi, T. Takewaki, T. Shibata, T. Ohmi, T. Nitta","doi":"10.1109/IEDM.1993.347354","DOIUrl":"https://doi.org/10.1109/IEDM.1993.347354","url":null,"abstract":"By using a simple pulsed-current stressing technique, we have demonstrated that both electromigration and stressmigration resistance of giant-grain Cu interconnects can be evaluated separately in a very efficient manner. From the results of such lifetests, it was found that the reliability of the the Cu interconnect is primarily determined by the stressmigration rather than by the electromigration.<<ETX>>","PeriodicalId":346650,"journal":{"name":"Proceedings of IEEE International Electron Devices Meeting","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126842978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Conducting filament of the programmed metal electrode amorphous silicon antifuse 程控金属电极非晶硅反熔丝的导电丝
Proceedings of IEEE International Electron Devices Meeting Pub Date : 1993-12-05 DOI: 10.1109/IEDM.1993.347406
Kathryn, Gordon, R. Wong
{"title":"Conducting filament of the programmed metal electrode amorphous silicon antifuse","authors":"Kathryn, Gordon, R. Wong","doi":"10.1109/IEDM.1993.347406","DOIUrl":"https://doi.org/10.1109/IEDM.1993.347406","url":null,"abstract":"Antifuses in PROM and FPGA applications have used silicon and/or polycrystalline silicon electrodes. Metal electrode antifuses have the lowest resistance and lowest capacitance among programmable interconnect structures. The ViaLink, a metal electrode amorphous silicon antifuse, has been used as a programmable interconnect device for a FPGA. This paper describes for the first time, the composition, structure, electrical characteristics, and temperature dependence of the conducting filament in the programmed TiW electrode amorphous silicon antifuse.<<ETX>>","PeriodicalId":346650,"journal":{"name":"Proceedings of IEEE International Electron Devices Meeting","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121108302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
Experimental studies of a 30 MW two-cavity second harmonic gyroklystron 30mw双腔二次谐波回旋速调管的实验研究
Proceedings of IEEE International Electron Devices Meeting Pub Date : 1993-12-05 DOI: 10.1109/IEDM.1993.347331
H. Matthews, W. Lawson, J. Calame, M. Flaherty, J. Cheng, B. Hogan, P. Latham, V. Granatstein
{"title":"Experimental studies of a 30 MW two-cavity second harmonic gyroklystron","authors":"H. Matthews, W. Lawson, J. Calame, M. Flaherty, J. Cheng, B. Hogan, P. Latham, V. Granatstein","doi":"10.1109/IEDM.1993.347331","DOIUrl":"https://doi.org/10.1109/IEDM.1993.347331","url":null,"abstract":"We report the operating characteristics of a sequence of two-cavity second harmonic K-band gyroklystrons. The TE/sub 011/ input cavity is driven near 9.88 GHz. The first four tubes utilized smooth transition output cavities which resonate at twice the drive frequency in the TE/sub 021/ mode. Peak powers in excess of 30 MW were achieved with efficiencies greater than 28% and large signal gains of 27 dB. The results of an abrupt transition complex TE/sub 01/, TE/sub 02/ mixed mode output cavity are also discussed, as well as the prospect of placing a coaxial insert into the highest power tube.<<ETX>>","PeriodicalId":346650,"journal":{"name":"Proceedings of IEEE International Electron Devices Meeting","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114754911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Monolithic CCD time-delay-and-integrate arrays in HgCdTe HgCdTe的单片CCD延时集成阵列
Proceedings of IEEE International Electron Devices Meeting Pub Date : 1993-12-05 DOI: 10.1109/IEDM.1993.347371
M. Wadsworth, S. Borrello, J. Dodge, R. Gooch, W. McCardel, G. Nado, Michael Dean Shilhanek
{"title":"Monolithic CCD time-delay-and-integrate arrays in HgCdTe","authors":"M. Wadsworth, S. Borrello, J. Dodge, R. Gooch, W. McCardel, G. Nado, Michael Dean Shilhanek","doi":"10.1109/IEDM.1993.347371","DOIUrl":"https://doi.org/10.1109/IEDM.1993.347371","url":null,"abstract":"Charge-coupled device (CCD) infrared detector arrays in 5 /spl mu/m cutoff HgCdTe have been demonstrated for low background applications. These fully monolithic CCD arrays incorporate time-delay-and-integrate (TDI) detection, serial readout multiplexing, charge-to-voltage conversion and buffer amplification in the HgCdTe detector chip. Performance data indicates the monolithic CCD to be a viable alternative to present hybrid focal plane array technology.<<ETX>>","PeriodicalId":346650,"journal":{"name":"Proceedings of IEEE International Electron Devices Meeting","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124302123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Lightly N/sub 2/O nitrided dielectrics grown in a conventional furnace for E/sup 2/PROM and 0.25 /spl mu/m CMOS 在传统电炉中生长的轻N/sub 2/O氮化电介质，用于E/sup 2/PROM和0.25 /spl μ m CMOS
Proceedings of IEEE International Electron Devices Meeting Pub Date : 1993-12-05 DOI: 10.1109/IEDM.1993.347310
H. Pomp, P. Woerlee, R. Woltjer, G. Paulzen, H. Lifka, A. Kuiper, J. D. de Zaldivar, S. Vecsernyes
{"title":"Lightly N/sub 2/O nitrided dielectrics grown in a conventional furnace for E/sup 2/PROM and 0.25 /spl mu/m CMOS","authors":"H. Pomp, P. Woerlee, R. Woltjer, G. Paulzen, H. Lifka, A. Kuiper, J. D. de Zaldivar, S. Vecsernyes","doi":"10.1109/IEDM.1993.347310","DOIUrl":"https://doi.org/10.1109/IEDM.1993.347310","url":null,"abstract":"For deep-submicron CMOS transistors and FLOTOX E/sup 2/PROM devices a considerable improvement in reliability and performance can be achieved when nitrided dielectrics are used. We developed an N/sup 2/O nitridation technology for a conventional furnace. Oxidation and nitridation are done in one run with a two-step and low-thermal budget processing to grow a dielectric layer with a thickness of 6-10 nm.<<ETX>>","PeriodicalId":346650,"journal":{"name":"Proceedings of IEEE International Electron Devices Meeting","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124418586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
TFSOI BiCMOS technology for low power applications 低功耗应用的TFSOI BiCMOS技术
Proceedings of IEEE International Electron Devices Meeting Pub Date : 1993-12-05 DOI: 10.1109/IEDM.1993.347313
W.M. Huang, K. Klein, M. Grimaldi, M. Racanelli, S. Ramaswami, T. Tsao, J. Foerstner, B. Hwang
{"title":"TFSOI BiCMOS technology for low power applications","authors":"W.M. Huang, K. Klein, M. Grimaldi, M. Racanelli, S. Ramaswami, T. Tsao, J. Foerstner, B. Hwang","doi":"10.1109/IEDM.1993.347313","DOIUrl":"https://doi.org/10.1109/IEDM.1993.347313","url":null,"abstract":"A thin film silicon on insulator BiCMOS technology has been developed for low power applications. The technology is based on a manufacturable, near-fully-depleted 0.5 /spl mu/m CMOS process with the lateral bipolar device integrated as a drop-in module for BiCMOS circuits. The bipolar device structure emphasizes use of a silicided polysilicon base contact to reduce base resistance and minimize current crowding effects. A split-oxide spacer integration is used to define the bipolar base and emitter widths independently. Low current ECL gate speeds up to 2/spl times/ faster than bulk double-polysilicon self-aligned bipolar circuits have been demonstrated.<<ETX>>","PeriodicalId":346650,"journal":{"name":"Proceedings of IEEE International Electron Devices Meeting","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124481997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Comparison of 80 nm-200 nm gate length Al/sub 0.25/GaAs/GaAs/Al/sub 0.25/GaAs, Al/sub 0.3/GaAs/In/sub 0.15/GaAs/GaAs and In/sub 0.52/AlAs/In/sub 0.65/GaAs/InP HEMTs 80 nm-200 nm栅极长度Al/sub 0.25/GaAs/GaAs/Al/sub 0.25/GaAs、Al/sub 0.3/GaAs/In/sub 0.15/GaAs/GaAs和In/sub 0.52/AlAs/In/sub 0.65/GaAs/InP HEMTs的比较
Proceedings of IEEE International Electron Devices Meeting Pub Date : 1993-12-05 DOI: 10.1109/IEDM.1993.347364
I. Thayne, M. Holland, Y. Chen, W. Li, A. Paulsen, S. Beaumont, P. Bhattacharya
{"title":"Comparison of 80 nm-200 nm gate length Al/sub 0.25/GaAs/GaAs/Al/sub 0.25/GaAs, Al/sub 0.3/GaAs/In/sub 0.15/GaAs/GaAs and In/sub 0.52/AlAs/In/sub 0.65/GaAs/InP HEMTs","authors":"I. Thayne, M. Holland, Y. Chen, W. Li, A. Paulsen, S. Beaumont, P. Bhattacharya","doi":"10.1109/IEDM.1993.347364","DOIUrl":"https://doi.org/10.1109/IEDM.1993.347364","url":null,"abstract":"This paper describes a comparative analysis of the high frequency performance of 80-200 nm gate length high electron mobility transistors (HEMTs) fabricated on three material structures having different 2 dimensional electron gas (2DEG) transport properties. The higher effective velocity of carriers in the channel of pseudomorphic InGaAs/InP devices resulted in 80 nm gate length devices with f/sub T/'s of 275 GHz. Device output resistance was found to be strongly material dependent. At the shortest gate lengths, the device f/sub max/ was limited primarily by the gate resistance. Additionally however, f/sub max/ was significantly affected by both the contribution of the gate drain capacitance to the total gate capacitance and the magnitude of the output resistance.<<ETX>>","PeriodicalId":346650,"journal":{"name":"Proceedings of IEEE International Electron Devices Meeting","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127729988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A new study of the junction leakage current due to 45/spl deg/-off active pattern after LOCOS process 对LOCOS工艺后45/spl度/关断有源模式引起的结漏电流进行了新的研究
Proceedings of IEEE International Electron Devices Meeting Pub Date : 1993-12-05 DOI: 10.1109/IEDM.1993.347206
M. Itoh, Y. Habutsu, S. Kuroda, Y. Nagatomo, M. Ino
{"title":"A new study of the junction leakage current due to 45/spl deg/-off active pattern after LOCOS process","authors":"M. Itoh, Y. Habutsu, S. Kuroda, Y. Nagatomo, M. Ino","doi":"10.1109/IEDM.1993.347206","DOIUrl":"https://doi.org/10.1109/IEDM.1993.347206","url":null,"abstract":"Influence of LOCOS process induced stress on junction leakage current is studied. The junction leakage current increases with increasing field oxide and Si/sub 3/N/sub 4/ film thickness. Furthermore the junction leakage current depends on active pattern direction. From evaluation of resolve shear stress for glide direction, the junction leakage current at the active edge inclined 45/spl deg/ to orientation flat is affected by shear stress more than that at active edge perpendicular to the flat. Origin of the junction leakage current is generation center produced by the shear stress.<<ETX>>","PeriodicalId":346650,"journal":{"name":"Proceedings of IEEE International Electron Devices Meeting","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134233890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Room temperature 0.1 /spl mu/m CMOS technology with 11.8 ps gate delay 室温0.1 /spl mu/m CMOS技术，栅极延迟11.8 ps
Proceedings of IEEE International Electron Devices Meeting Pub Date : 1993-12-05 DOI: 10.1109/IEDM.1993.347382
K. Lee, R. Yan, D. Jeon, G. Chin, Y.O. Kim, D. Tennant, B. Razavi, H. Lin, Y. Wey, E. Westerwick, M. Morris, R.W. Johnson, T.M. Liu, M. Tarsia, M. Cerullo, R. Swartz, A. Ourmazd
{"title":"Room temperature 0.1 /spl mu/m CMOS technology with 11.8 ps gate delay","authors":"K. Lee, R. Yan, D. Jeon, G. Chin, Y.O. Kim, D. Tennant, B. Razavi, H. Lin, Y. Wey, E. Westerwick, M. Morris, R.W. Johnson, T.M. Liu, M. Tarsia, M. Cerullo, R. Swartz, A. Ourmazd","doi":"10.1109/IEDM.1993.347382","DOIUrl":"https://doi.org/10.1109/IEDM.1993.347382","url":null,"abstract":"We report a room temperature, 0.1 /spl mu/m CMOS technology on bulk Si substrates that delivers a record ring-oscillator gate delay of 11.8 psec at 2.5 V. Frequency dividers at 2.0 V operate with input frequencies exceeding 8.5 GHz. Feature sizes obey g-line lithography design rules except at the gate level. The high speed CMOS performance and the good subthreshold and drain characteristics for both NMOS and PMOS devices are obtained through the implementation of vertical doping engineering and the reduction of parasitics.<<ETX>>","PeriodicalId":346650,"journal":{"name":"Proceedings of IEEE International Electron Devices Meeting","volume":"7 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134447339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 51
Vertical profile optimization of very high frequency epitaxial Si- and SiGe-base bipolar transistors 甚高频外延硅基和硅基双极晶体管的垂直轮廓优化
Proceedings of IEEE International Electron Devices Meeting Pub Date : 1993-12-05 DOI: 10.1109/IEDM.1993.347393
E. Crabbé, B. Meyerson, J. Stork, D. Harame
{"title":"Vertical profile optimization of very high frequency epitaxial Si- and SiGe-base bipolar transistors","authors":"E. Crabbé, B. Meyerson, J. Stork, D. Harame","doi":"10.1109/IEDM.1993.347393","DOIUrl":"https://doi.org/10.1109/IEDM.1993.347393","url":null,"abstract":"Bipolar transistors with phosphorus-doped emitters and sub-50 nm epitaxial bases have been fabricated in a low thermal-cycle process to explore the trade-offs between cutoff frequency, breakdown voltage and Early voltage. Record peak f/sub T/s of 73 GHz for a Si BJT and 113 GHz for a SiGe HBT with respective /spl beta/V/sub A/ products of 630 and 48,400 V were obtained for intrinsic base sheet resistances of 26 and 7 k/spl Omega/spl square/.<<ETX>>","PeriodicalId":346650,"journal":{"name":"Proceedings of IEEE International Electron Devices Meeting","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134449736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 81
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