W.M. Huang, K. Klein, M. Grimaldi, M. Racanelli, S. Ramaswami, T. Tsao, J. Foerstner, B. Hwang
{"title":"TFSOI BiCMOS technology for low power applications","authors":"W.M. Huang, K. Klein, M. Grimaldi, M. Racanelli, S. Ramaswami, T. Tsao, J. Foerstner, B. Hwang","doi":"10.1109/IEDM.1993.347313","DOIUrl":null,"url":null,"abstract":"A thin film silicon on insulator BiCMOS technology has been developed for low power applications. The technology is based on a manufacturable, near-fully-depleted 0.5 /spl mu/m CMOS process with the lateral bipolar device integrated as a drop-in module for BiCMOS circuits. The bipolar device structure emphasizes use of a silicided polysilicon base contact to reduce base resistance and minimize current crowding effects. A split-oxide spacer integration is used to define the bipolar base and emitter widths independently. Low current ECL gate speeds up to 2/spl times/ faster than bulk double-polysilicon self-aligned bipolar circuits have been demonstrated.<<ETX>>","PeriodicalId":346650,"journal":{"name":"Proceedings of IEEE International Electron Devices Meeting","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of IEEE International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.1993.347313","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 14
Abstract
A thin film silicon on insulator BiCMOS technology has been developed for low power applications. The technology is based on a manufacturable, near-fully-depleted 0.5 /spl mu/m CMOS process with the lateral bipolar device integrated as a drop-in module for BiCMOS circuits. The bipolar device structure emphasizes use of a silicided polysilicon base contact to reduce base resistance and minimize current crowding effects. A split-oxide spacer integration is used to define the bipolar base and emitter widths independently. Low current ECL gate speeds up to 2/spl times/ faster than bulk double-polysilicon self-aligned bipolar circuits have been demonstrated.<>