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Oxygen plasma enhanced crystallization of a-Si for low thermal budget poly-Si TFTs on Corning 7059 glass 氧等离子体增强在康宁7059玻璃上的低热收支多晶硅tft的a-Si结晶
Proceedings of IEEE International Electron Devices Meeting Pub Date : 1993-12-05 DOI: 10.1109/IEDM.1993.347325
A. Yin, S. Fonash
{"title":"Oxygen plasma enhanced crystallization of a-Si for low thermal budget poly-Si TFTs on Corning 7059 glass","authors":"A. Yin, S. Fonash","doi":"10.1109/IEDM.1993.347325","DOIUrl":"https://doi.org/10.1109/IEDM.1993.347325","url":null,"abstract":"A new fabrication process for advanced polycrystalline silicon thin film transistors on 7059 glass substrates has been developed. This unique fabrication process has the advantage of short processing time at low processing temperatures (/spl les/600/spl deg/C). The processing is based on the key step of an oxygen plasma treatment of precursor amorphous silicon (a-Si) films prior to crystallization. This plasma treatment enhances the thermal crystallization process and reduces the crystallization thermal budget substantially. The viability of this new crystallization process is demonstrated with n-channel thin film transistors with mobility values of 35 cm/sup 2V s, on/off current ratios 4/spl times/10/sup 6/ and threshold voltages of 0.5 V.<<ETX>>","PeriodicalId":346650,"journal":{"name":"Proceedings of IEEE International Electron Devices Meeting","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129990664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Degradation-free Ta/sub 2/O/sub 5/ capacitor after BPSG reflow at 850/spl deg/C for high density DRAMs 用于高密度dram的BPSG在850/spl度/C回流后无退化的Ta/sub 2/O/sub 5/电容器
Proceedings of IEEE International Electron Devices Meeting Pub Date : 1993-12-05 DOI: 10.1109/IEDM.1993.347400
K. Kwon, S. Park, C. Kang, Y.N. Kim, S.T. Ahn, M.Y. Lee
{"title":"Degradation-free Ta/sub 2/O/sub 5/ capacitor after BPSG reflow at 850/spl deg/C for high density DRAMs","authors":"K. Kwon, S. Park, C. Kang, Y.N. Kim, S.T. Ahn, M.Y. Lee","doi":"10.1109/IEDM.1993.347400","DOIUrl":"https://doi.org/10.1109/IEDM.1993.347400","url":null,"abstract":"The thermal degradation of the Ta/sub 2/O/sub 5/ capacitor during BPSG reflow has been studied. The cause of deterioration of Ta/sub 2/O/sub 5/ with the TiN top electrode was found to be the oxidation of TiN. By inserting poly-Si between TiN and BPSG to suppress oxidation, the low leakage current level was maintained after BPSG reflow at 850/spl deg/C. The Ta/sub 2/O/sub 5/ capacitor with the TiN/poly-Si top electrode was integrated into 64 Mbit DRAMs and excellent leakage current characteristics were obtained.<<ETX>>","PeriodicalId":346650,"journal":{"name":"Proceedings of IEEE International Electron Devices Meeting","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130003036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 1/4 inch 380 k pixel IT-CCD image sensor employing gate-assisted punchthrough read-out mode 采用门辅助穿孔读出模式的1/4英寸380 k像素IT-CCD图像传感器
Proceedings of IEEE International Electron Devices Meeting Pub Date : 1993-12-05 DOI: 10.1109/IEDM.1993.347287
N. Mutoh, K. Orihara, Y. Kawakami, T. Nakano, S. Kawai, I. Murakami, A. Tanabe, S. Suwazono, K. Arai, N. Teranishi, M. Furumiya, M. Morimoto, K. Hatano, K. Minami, Y. Hokari
{"title":"A 1/4 inch 380 k pixel IT-CCD image sensor employing gate-assisted punchthrough read-out mode","authors":"N. Mutoh, K. Orihara, Y. Kawakami, T. Nakano, S. Kawai, I. Murakami, A. Tanabe, S. Suwazono, K. Arai, N. Teranishi, M. Furumiya, M. Morimoto, K. Hatano, K. Minami, Y. Hokari","doi":"10.1109/IEDM.1993.347287","DOIUrl":"https://doi.org/10.1109/IEDM.1993.347287","url":null,"abstract":"The authors propose a new cell structure employing a gate-assisted punchthrough read-out mode, which is suitable for a high packing density interline-transfer CCD (IT-CCD) image sensor. The new cell structure, fabricated through the use of high energy ion implantation technology, enables both deep photodiode formation and transfer-gate/ channel-stop length reduction. The proposed structure has been applied to a 1/4 inch 380 k pixel IT-CCD image sensor with reduced pixel size as small as 4.8 /spl mu/m (H)/spl times/5.6 /spl mu/m (V), which attains a high sensitivity (35 mV/lx) and a large saturation signal (600 mV).<<ETX>>","PeriodicalId":346650,"journal":{"name":"Proceedings of IEEE International Electron Devices Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129511730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Tunable internal photoemission sensor using silicide/silicon heterostructures
Proceedings of IEEE International Electron Devices Meeting Pub Date : 1993-12-05 DOI: 10.1109/IEDM.1993.347252
I. Sagnes, Y. Campidelli, F. Chevalier, P.A. Badoz
{"title":"Tunable internal photoemission sensor using silicide/silicon heterostructures","authors":"I. Sagnes, Y. Campidelli, F. Chevalier, P.A. Badoz","doi":"10.1109/IEDM.1993.347252","DOIUrl":"https://doi.org/10.1109/IEDM.1993.347252","url":null,"abstract":"A new silicide/silicon IR detector is presented which has the potential for multicolor detection due to the tunability of its photoresponse and cutoff wavelength. This tunable internal photoemission sensor (TIPS) consists of two back-to-back Schottky diodes separated by a thin undoped Si layer. The two metals are chosen with different Schottky barrier heights so that the depleted Si forms an asymmetrical potential barrier to the carriers (both holes and electrons) photocreated in each metallic film. Under sub-band gap illumination the photocurrent flowing between the two metallic films is therefore strongly dependent on the shape and height of the potential barrier which can be varied by a small bias applied between the two metal electrodes.<<ETX>>","PeriodicalId":346650,"journal":{"name":"Proceedings of IEEE International Electron Devices Meeting","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129781761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A physical poly-silicon thin film transistor model for circuit simulations 用于电路仿真的多晶硅薄膜晶体管物理模型
Proceedings of IEEE International Electron Devices Meeting Pub Date : 1993-12-05 DOI: 10.1109/IEDM.1993.347302
C. Li, K. Ikeda, T. Inoue, P. Ko
{"title":"A physical poly-silicon thin film transistor model for circuit simulations","authors":"C. Li, K. Ikeda, T. Inoue, P. Ko","doi":"10.1109/IEDM.1993.347302","DOIUrl":"https://doi.org/10.1109/IEDM.1993.347302","url":null,"abstract":"This paper presents a poly-silicon thin film transistor model for circuit simulations. The drain current model includes the effects of hot carriers, drain induced barrier lowering (DIBL), channel length modulation (CLM), and gate induced drain leakage (GIDL). The capacitance model is weakly linked to the drain current and its derivatives. This model has been implemented in a SPICE simulation and experimental results are compared.<<ETX>>","PeriodicalId":346650,"journal":{"name":"Proceedings of IEEE International Electron Devices Meeting","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127551917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Polysilicon resistor trimming for packaged integrated circuits 封装集成电路用多晶硅电阻修整
Proceedings of IEEE International Electron Devices Meeting Pub Date : 1993-12-05 DOI: 10.1109/IEDM.1993.347359
J. Babcock, D. W. Feldbaumer, V. M. Mercier
{"title":"Polysilicon resistor trimming for packaged integrated circuits","authors":"J. Babcock, D. W. Feldbaumer, V. M. Mercier","doi":"10.1109/IEDM.1993.347359","DOIUrl":"https://doi.org/10.1109/IEDM.1993.347359","url":null,"abstract":"Pulse current trimming to adjust values of polysilicon resistors has been investigated for use in full scale IC production. The technique is remarkably accurate, layout efficient, quick and inexpensive from a test perspective, and requires no additional process complexity. The trim process is shown to be reversible to a small, but usable extent for n-type polysilicon. A new physical model consistent with all observations for resistance trim and recovery is presented. Finally, reliability results from extensive burn-in show the trimmed resistors to be exceptionally robust.<<ETX>>","PeriodicalId":346650,"journal":{"name":"Proceedings of IEEE International Electron Devices Meeting","volume":"280 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121255364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
3D modeling of contact material deposition and its impact on equipment design parameters 接触材料沉积的三维建模及其对设备设计参数的影响
Proceedings of IEEE International Electron Devices Meeting Pub Date : 1993-12-05 DOI: 10.1109/IEDM.1993.347264
F. Baumann, R. Liu, C. B. Case, W. Lai
{"title":"3D modeling of contact material deposition and its impact on equipment design parameters","authors":"F. Baumann, R. Liu, C. B. Case, W. Lai","doi":"10.1109/IEDM.1993.347264","DOIUrl":"https://doi.org/10.1109/IEDM.1993.347264","url":null,"abstract":"We report the first full 3D simulations of conventional and collimated sputter deposition into high aspect ratio windows and vias, which accurately reproduce all features of experimental data. First, a 3D Monte Carlo approach is employed to simulate the microscopic structure of the films and the evolution of the topography during deposition. Second, a 3D geometric calculation investigates how macroscopic effects (film thicknesses under the collimator, shadowing, collimator transmission) vary with collimation parameters, such as grid size and position. The results are used to determine optimum equipment design.<<ETX>>","PeriodicalId":346650,"journal":{"name":"Proceedings of IEEE International Electron Devices Meeting","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123061087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Modeling on increase of n-p-n and p-n-p current gain by hydrogen electromigration in polysilicon emitters 多晶硅发射体中氢电迁移增加n-p-n和p-n-p电流增益的建模
Proceedings of IEEE International Electron Devices Meeting Pub Date : 1993-12-05 DOI: 10.1109/IEDM.1993.347288
J. Zhao, G. Li, K. Liao, M. Chin, J. Sun, P. Ratnam
{"title":"Modeling on increase of n-p-n and p-n-p current gain by hydrogen electromigration in polysilicon emitters","authors":"J. Zhao, G. Li, K. Liao, M. Chin, J. Sun, P. Ratnam","doi":"10.1109/IEDM.1993.347288","DOIUrl":"https://doi.org/10.1109/IEDM.1993.347288","url":null,"abstract":"A unified analytical model that relates the increase of current gain to forward current stress is presented for both poly emitter n-p-n and p-n-p transistors. This model is based on electromigration of atomic hydrogen and its subsequent passivation of dangling bonds at polysilicon grain boundaries and poly/mono-silicon interface. The comparison between experiment and simulation results is also presented.<<ETX>>","PeriodicalId":346650,"journal":{"name":"Proceedings of IEEE International Electron Devices Meeting","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120879395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
High transconductance n- and p-channel GaAs MESFETs using novel amphipolar Cu/sub 3/Ge ohmic contacts 采用新型双极Cu/sub /Ge欧姆触点的高跨导n沟道和p沟道GaAs mesfet
Proceedings of IEEE International Electron Devices Meeting Pub Date : 1993-12-05 DOI: 10.1109/IEDM.1993.347250
C. Lin, M. O. Aboelfotoh, J. Woodall, E. Lin, W. Ku, M. Melloch
{"title":"High transconductance n- and p-channel GaAs MESFETs using novel amphipolar Cu/sub 3/Ge ohmic contacts","authors":"C. Lin, M. O. Aboelfotoh, J. Woodall, E. Lin, W. Ku, M. Melloch","doi":"10.1109/IEDM.1993.347250","DOIUrl":"https://doi.org/10.1109/IEDM.1993.347250","url":null,"abstract":"In this paper, we present results of n- and p-MESFETs using one ohmic contact metallurgy, Cu/sub 3/Ge, which was first introduced by Aboelfotoh. Cu/sub 3/Ge makes an ohmic contact to both n- and p-type GaAs at typical doping levels for device applications. The amphipolar nature of this ohmic contact formation will be discussed elsewhere. These contacts exhibit very low contact resistance and do not suffer from lateral spreading during high temperature annealing (500 C). In addition, their uniformity and reproducibility allow reliable fabrication of high-density sub-micron devices.<<ETX>>","PeriodicalId":346650,"journal":{"name":"Proceedings of IEEE International Electron Devices Meeting","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113940509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Symmetric CMOS in fully-depleted silicon-on-insulator using P/sup +/-polycrystalline SiGe gate electrodes 对称CMOS在完全耗尽的绝缘体上的硅使用P/sup +/-多晶SiGe栅极
Proceedings of IEEE International Electron Devices Meeting Pub Date : 1993-12-05 DOI: 10.1109/IEDM.1993.347210
N. Kistler, J. Woo
{"title":"Symmetric CMOS in fully-depleted silicon-on-insulator using P/sup +/-polycrystalline SiGe gate electrodes","authors":"N. Kistler, J. Woo","doi":"10.1109/IEDM.1993.347210","DOIUrl":"https://doi.org/10.1109/IEDM.1993.347210","url":null,"abstract":"In this work, polycrystalline SiGe gate electrodes have been implemented on fully-depleted silicon-on-insulator with light channel doping. Symmetric NMOS and PMOS operation is achieved, with threshold voltages in the range of 0.4-0.6 V. The devices exhibit good short-channel behavior and near-ideal subthreshold slope. CMOS ring oscillators with enhancement-mode NMOS and PMOS have been fabricated, exhibiting propagation delays comparable to previously reported values for fully-depleted SOI.<<ETX>>","PeriodicalId":346650,"journal":{"name":"Proceedings of IEEE International Electron Devices Meeting","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132413114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
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