A physical poly-silicon thin film transistor model for circuit simulations

Proceedings of IEEE International Electron Devices Meeting Pub Date : 1993-12-05 DOI:10.1109/IEDM.1993.347302

C. Li, K. Ikeda, T. Inoue, P. Ko

引用次数: 10

Abstract

This paper presents a poly-silicon thin film transistor model for circuit simulations. The drain current model includes the effects of hot carriers, drain induced barrier lowering (DIBL), channel length modulation (CLM), and gate induced drain leakage (GIDL). The capacitance model is weakly linked to the drain current and its derivatives. This model has been implemented in a SPICE simulation and experimental results are compared.<>

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用于电路仿真的多晶硅薄膜晶体管物理模型

本文提出了一种用于电路仿真的多晶硅薄膜晶体管模型。漏极电流模型包括热载流子、漏极诱导势垒降低(DIBL)、通道长度调制(CLM)和栅极诱导漏极泄漏(GIDL)的影响。电容模型与漏极电流及其导数的关系很弱。该模型已在SPICE仿真中实现，并对实验结果进行了比较。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings of IEEE International Electron Devices Meeting

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