发布求助
文献互助 智能选刊 最新文献

27th International Spring Seminar on Electronics Technology: Meeting the Challenges of Electronics Technology Progress, 2004.最新文献

筛选
英文 中文
Complex evaluation of SMT defects SMT缺陷的复杂评估
27th International Spring Seminar on Electronics Technology: Meeting the Challenges of Electronics Technology Progress, 2004. Pub Date : 2004-05-13 DOI: 10.1109/ISSE.2004.1490375
D. Simon-Zanescu, F. Streza, P. Svasta
{"title":"Complex evaluation of SMT defects","authors":"D. Simon-Zanescu, F. Streza, P. Svasta","doi":"10.1109/ISSE.2004.1490375","DOIUrl":"https://doi.org/10.1109/ISSE.2004.1490375","url":null,"abstract":"Soldering process through reflow ovens is a well repeatable work. Once a thermal profile is establish for an oven and any parameters regarding the assembly process do not change, the results are quite identical for each board passing through the oven. The situation is different when other kinds of board are passed through. The usual solution to solving these parameter changes is to do many trials. But for small and diverse production, that is expensive. We try to solve this problem by creating a self teaching application which can predict the parameters of the process starting from board parameters and previous experience. The primary key of this application is to take correct decisions and build the shell matrix of cause-and-effect. That is the aim of the paper.","PeriodicalId":342004,"journal":{"name":"27th International Spring Seminar on Electronics Technology: Meeting the Challenges of Electronics Technology Progress, 2004.","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115762279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Technical requirements in enterprise resource planning systems 企业资源规划系统的技术要求
27th International Spring Seminar on Electronics Technology: Meeting the Challenges of Electronics Technology Progress, 2004. Pub Date : 2004-05-13 DOI: 10.1109/ISSE.2004.1490857
Zoltan SZlTAS
{"title":"Technical requirements in enterprise resource planning systems","authors":"Zoltan SZlTAS","doi":"10.1109/ISSE.2004.1490857","DOIUrl":"https://doi.org/10.1109/ISSE.2004.1490857","url":null,"abstract":"An enterprise resource planning (ERP) system is defined as a unified information system, performing all information-processing tasks of a company and realizing an integration of the whole corporation. The aimed scope of duties indicates that these software products are very complex regarding their structure and operation. What is more, ERP systems are almost always standard software products. The parametrizable and configurable structure increases their complexity. We analyse these complex software products. We examine the users' needs and the life-cycle of these systems, determine their components according to the three tier architecture and summarize the requirements against these parts.","PeriodicalId":342004,"journal":{"name":"27th International Spring Seminar on Electronics Technology: Meeting the Challenges of Electronics Technology Progress, 2004.","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125127010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Design of experiments (DOE) of automatic soldering process "wave soldering" 自动焊接工艺“波峰焊”实验设计(DOE)
27th International Spring Seminar on Electronics Technology: Meeting the Challenges of Electronics Technology Progress, 2004. Pub Date : 2004-05-13 DOI: 10.1109/ISSE.2004.1490447
V. Tsenev, L. Marinov
{"title":"Design of experiments (DOE) of automatic soldering process \"wave soldering\"","authors":"V. Tsenev, L. Marinov","doi":"10.1109/ISSE.2004.1490447","DOIUrl":"https://doi.org/10.1109/ISSE.2004.1490447","url":null,"abstract":"DOE is a method for improving technological processes after it is proved that they are under control. What is most important about this method is that it requires minimum resources at a moderate risk level. The report describes the application of this method to reduce the defects during automatic soldering of electronic components on a printed circuit board by the \"wave soldering\" process. The input of the process is being influenced only. A mathematical model, based on matrix calculations, is being used in the report.","PeriodicalId":342004,"journal":{"name":"27th International Spring Seminar on Electronics Technology: Meeting the Challenges of Electronics Technology Progress, 2004.","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125932360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
The influence of technological process on properties and reliability of thick film layers 工艺过程对厚膜层性能和可靠性的影响
27th International Spring Seminar on Electronics Technology: Meeting the Challenges of Electronics Technology Progress, 2004. Pub Date : 2004-05-13 DOI: 10.1109/ISSE.2004.1490444
I. Pelikánová, T. Konupka
{"title":"The influence of technological process on properties and reliability of thick film layers","authors":"I. Pelikánová, T. Konupka","doi":"10.1109/ISSE.2004.1490444","DOIUrl":"https://doi.org/10.1109/ISSE.2004.1490444","url":null,"abstract":"Thick film layers, and their properties, are the topic of this paper. Attention is paid to thick film resistors and particularly their behavior in connection with the trimming process. The influence of two methods of trimming was investigated and compared. Some samples were trimmed by a milling cutter and other samples were trimmed by laser. The change of resistance and non linearity of C-V characteristics were measured.","PeriodicalId":342004,"journal":{"name":"27th International Spring Seminar on Electronics Technology: Meeting the Challenges of Electronics Technology Progress, 2004.","volume":"367 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123408183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
SPICE modeling of MOSFETs in deep submicron 深亚微米mosfet的SPICE建模
27th International Spring Seminar on Electronics Technology: Meeting the Challenges of Electronics Technology Progress, 2004. Pub Date : 2004-05-13 DOI: 10.1109/ISSE.2004.1490430
G. Angelov, M. Hristov
{"title":"SPICE modeling of MOSFETs in deep submicron","authors":"G. Angelov, M. Hristov","doi":"10.1109/ISSE.2004.1490430","DOIUrl":"https://doi.org/10.1109/ISSE.2004.1490430","url":null,"abstract":"As the mainstream MOS technology is scaling into nanometer sizes, the development of physical and predictive models for circuit simulation that cover geometry, bias, temperature, DC, AC, RF, and noise characteristics becomes a major goal. The paper addresses the scaling, trends and their limiting factors and follows through the evolution of the three MOSFET model generations of SPICE: from the Berkeley Levels 1, 2, 3 to the latest BSIM3v3, BSIM4, MM11, EKV, and SP2001. MOSFET models are examined, emphasizing device physics and mathematical techniques for numerical calculation.","PeriodicalId":342004,"journal":{"name":"27th International Spring Seminar on Electronics Technology: Meeting the Challenges of Electronics Technology Progress, 2004.","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123410776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Graphical user interface logical schemes design tool [educational tool] 图形用户界面逻辑方案设计工具【教育工具】
27th International Spring Seminar on Electronics Technology: Meeting the Challenges of Electronics Technology Progress, 2004. Pub Date : 2004-05-13 DOI: 10.1109/ISSE.2004.1490454
V. Mateev, P. Manoilov
{"title":"Graphical user interface logical schemes design tool [educational tool]","authors":"V. Mateev, P. Manoilov","doi":"10.1109/ISSE.2004.1490454","DOIUrl":"https://doi.org/10.1109/ISSE.2004.1490454","url":null,"abstract":"The beginning of a new intelligent interactive tool for education in the area of logical circuit design is presented in this article. The educational tool has a library with logical elements and a graphic area for the students to create the scheme of Boolean functions given in advance. The artificial intelligence module has the possibility to estimate the correctness of the decision, presented by the student. The Java programming language has been used which allows us to create a stand-alone application, an integrate platform (computer hardware and operating system), and put browser independent features into Web documents.","PeriodicalId":342004,"journal":{"name":"27th International Spring Seminar on Electronics Technology: Meeting the Challenges of Electronics Technology Progress, 2004.","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114438384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low-voltage FIR filter for receivers used in communication systems 用于通信系统接收机的低压FIR滤波器
27th International Spring Seminar on Electronics Technology: Meeting the Challenges of Electronics Technology Progress, 2004. Pub Date : 2004-05-13 DOI: 10.1109/ISSE.2004.1490850
L. Lita, D. Visan, I. B. Cioc, L. Banica
{"title":"Low-voltage FIR filter for receivers used in communication systems","authors":"L. Lita, D. Visan, I. B. Cioc, L. Banica","doi":"10.1109/ISSE.2004.1490850","DOIUrl":"https://doi.org/10.1109/ISSE.2004.1490850","url":null,"abstract":"The paper presents the principle and a possible implementation for an improved finite-impulse response (FIR) filter intended to be used with receivers operating in low voltage supply conditions. Basically, the main application of this filter is in the equalizer building block of a wireless receiver. To provide the filter with simple programmability through digital words, current dividers based on MOS transistors are included in its structure. Also, a very important block of the presented filter includes sample/hold circuits that must work at the same low supply voltage as the entire system. Low voltage operation of the proposed filter is achieved using the switched current technique.","PeriodicalId":342004,"journal":{"name":"27th International Spring Seminar on Electronics Technology: Meeting the Challenges of Electronics Technology Progress, 2004.","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129588532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
FPGA implementation of bit timing logic of CAN controller CAN控制器位时序逻辑的FPGA实现
27th International Spring Seminar on Electronics Technology: Meeting the Challenges of Electronics Technology Progress, 2004. Pub Date : 2004-05-13 DOI: 10.1109/ISSE.2004.1490422
P. Dzhelekarski, V. Zerbe, D. Alexiev
{"title":"FPGA implementation of bit timing logic of CAN controller","authors":"P. Dzhelekarski, V. Zerbe, D. Alexiev","doi":"10.1109/ISSE.2004.1490422","DOIUrl":"https://doi.org/10.1109/ISSE.2004.1490422","url":null,"abstract":"A controller area network (CAN) protocol has two layers, physical layer and data link layer (DLL). The upper sub-layers of the physical layer, called physical signaling, and DLL are normally incorporated in CAN controllers. The paper describes the implementation of the bit timing logic of a CAN controller on an Altera/spl reg/ Stratix/spl trade/ FPGA board. The bit timing logic corresponds to the physical signaling sub-layer and is implemented as a schematic using Quartus/spl reg/ II Block Diagram Editor. The module is built up of 3 prescalers, PLL, synchronization logic and receiving/transmitting logic.","PeriodicalId":342004,"journal":{"name":"27th International Spring Seminar on Electronics Technology: Meeting the Challenges of Electronics Technology Progress, 2004.","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130608664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Numerical simulation of selected semiconductor devices 所选半导体器件的数值模拟
27th International Spring Seminar on Electronics Technology: Meeting the Challenges of Electronics Technology Progress, 2004. Pub Date : 2004-05-13 DOI: 10.1109/ISSE.2004.1490390
V. Palankovski, S. Selberherr
{"title":"Numerical simulation of selected semiconductor devices","authors":"V. Palankovski, S. Selberherr","doi":"10.1109/ISSE.2004.1490390","DOIUrl":"https://doi.org/10.1109/ISSE.2004.1490390","url":null,"abstract":"We present a review of industrial heterostructure devices, based on SiGe/Si and III-V compound semiconductors, analyzed by means of numerical simulation. Critical modeling issues are addressed. Results from 2D hydrodynamic analyses of heterojunction bipolar transistors (HBTs) and field-effect transistors (FETs) are presented, and are in good agreement with measured data.","PeriodicalId":342004,"journal":{"name":"27th International Spring Seminar on Electronics Technology: Meeting the Challenges of Electronics Technology Progress, 2004.","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130678822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Integrated scheduling of heterogeneous CAN and Ethernet-based hard real-time network 基于CAN和以太网的异构硬实时网络综合调度
27th International Spring Seminar on Electronics Technology: Meeting the Challenges of Electronics Technology Progress, 2004. Pub Date : 2004-05-13 DOI: 10.1109/ISSE.2004.1490861
I. E. Ivanov, K.W. Filipowa
{"title":"Integrated scheduling of heterogeneous CAN and Ethernet-based hard real-time network","authors":"I. E. Ivanov, K.W. Filipowa","doi":"10.1109/ISSE.2004.1490861","DOIUrl":"https://doi.org/10.1109/ISSE.2004.1490861","url":null,"abstract":"This paper discusses some problems in scheduling heterogeneous Ethernet/CAN real-time networks. Modification of standard Ethernet-based communication subsystem to token-ring, flow-chart and its corresponding Petri-net are provided. Analyses of protocol structure, concurrences, possible raised conditions and methods for their suppression are main target of the paper. Integrated structure of Ethernet/CAN real-time communication subsystem is also analyzed.","PeriodicalId":342004,"journal":{"name":"27th International Spring Seminar on Electronics Technology: Meeting the Challenges of Electronics Technology Progress, 2004.","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130682167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信