FPGA implementation of bit timing logic of CAN controller

Abstract

A controller area network (CAN) protocol has two layers, physical layer and data link layer (DLL). The upper sub-layers of the physical layer, called physical signaling, and DLL are normally incorporated in CAN controllers. The paper describes the implementation of the bit timing logic of a CAN controller on an Altera/spl reg/ Stratix/spl trade/ FPGA board. The bit timing logic corresponds to the physical signaling sub-layer and is implemented as a schematic using Quartus/spl reg/ II Block Diagram Editor. The module is built up of 3 prescalers, PLL, synchronization logic and receiving/transmitting logic.