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2012 IEEE International Reliability Physics Symposium (IRPS)最新文献

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Critical temperature shift for Stress Induced Voiding in advanced Cu interconnects for 32 nm and beyond 在32纳米及以上的先进铜互连中应力诱导空化的临界温度变化
2012 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2012-04-15 DOI: 10.1109/IRPS.2012.6241901
Rao R. Morusupalli, R. Rao, Tae-Kyu Lee, Yu‐Lin Shen, M. Kunz, N. Tamura, A. Budiman
{"title":"Critical temperature shift for Stress Induced Voiding in advanced Cu interconnects for 32 nm and beyond","authors":"Rao R. Morusupalli, R. Rao, Tae-Kyu Lee, Yu‐Lin Shen, M. Kunz, N. Tamura, A. Budiman","doi":"10.1109/IRPS.2012.6241901","DOIUrl":"https://doi.org/10.1109/IRPS.2012.6241901","url":null,"abstract":"In this paper we present work showing evidence of a shift in the Stress Migration (SM) peak profile temperature for smaller interconnect linewidths typically associated with the 32 nm technology node and beyond. With other parameters (fabrication, materials, line thickness and via diameter being kept nominal among these samples), this clear shift towards the lower temperatures for smaller linewidths appear to indicate a size effect in the Stress Migration in advanced Cu interconnect scheme. Through the synchrotron x-ray micro-diffraction experiment, we show that plasticity is involved in the stress relaxation process at about 200 C, but not at higher temperature nor at room temperature. Such plasticity-assisted strain relaxation in interconnects especially at lower temperature range could explain the critical temperature shift observed in the present study, in addition to the typical diffusion-assisted mechanism. In conjunction with the experimental study, numerical finite element analyses were also conducted to provide greater insight. The modeling result demonstrates the importance of creep plasticity in causing thermal stress relaxation in Cu interconnects.","PeriodicalId":341663,"journal":{"name":"2012 IEEE International Reliability Physics Symposium (IRPS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126342896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Clarification of the degradation modes of an InP-based semiconductor MZ modulator 阐明了一种基于inp的半导体MZ调制器的退化模式
2012 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2012-04-15 DOI: 10.1109/IRPS.2012.6241884
H. Mawatari, T. Yasui, K. Watanabe, M. Ishikawa, E. Yamada, Y. Shibata, H. Ishii
{"title":"Clarification of the degradation modes of an InP-based semiconductor MZ modulator","authors":"H. Mawatari, T. Yasui, K. Watanabe, M. Ishikawa, E. Yamada, Y. Shibata, H. Ishii","doi":"10.1109/IRPS.2012.6241884","DOIUrl":"https://doi.org/10.1109/IRPS.2012.6241884","url":null,"abstract":"We clarified the degradation modes of an InP-based semiconductor optical Mach-Zehnder modulator (MZM) using high-power light-injected accelerated aging tests. Degradation clearly occurred at the light injected side of the edge on the electric field applied region. We found that the degradation threshold depends strongly on temperature, wavelength and bias voltage. By correlating these parameters, we propose a degradation model based on the concentration of the optical absorption current, which depends on the optical absorption coefficient. By employing the degradation model, we obtained the degradation activation energy for a semiconductor MZM for the first time, and the value was 0.45 eV. These results indicate that a semiconductor MZM is sufficiently reliable for use in actual optical communication systems.","PeriodicalId":341663,"journal":{"name":"2012 IEEE International Reliability Physics Symposium (IRPS)","volume":"9 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131695850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Impact of hot electrons on the reliability of AlGaN/GaN High Electron Mobility Transistors 热电子对AlGaN/GaN高电子迁移率晶体管可靠性的影响
2012 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2012-04-15 DOI: 10.1109/IRPS.2012.6241779
M. Meneghini, A. Stocco, R. Silvestri, N. Ronchi, G. Meneghesso, E. Zanoni
{"title":"Impact of hot electrons on the reliability of AlGaN/GaN High Electron Mobility Transistors","authors":"M. Meneghini, A. Stocco, R. Silvestri, N. Ronchi, G. Meneghesso, E. Zanoni","doi":"10.1109/IRPS.2012.6241779","DOIUrl":"https://doi.org/10.1109/IRPS.2012.6241779","url":null,"abstract":"This paper reports on an extensive analysis of the degradation of AlGaN/GaN HEMTs submitted to on-state stress tests. By means of combined electrical and electroluminescence characterization we demonstrate that: (i) exposure to on-state stress can induce a remarkable decrease in drain current; (ii) degradation rate strongly depends on the intensity of the EL signal emitted by the devices during stress, while it has a negligible dependence on temperature. On the basis of the experimental evidence collected within this work, degradation is ascribed to electron trapping in the gate-drain access region, induced by hot electrons. Finally, we derived an acceleration law for GaN HEMT degradation, by using the intensity of the EL signal as a measure of the stress acceleration factor.","PeriodicalId":341663,"journal":{"name":"2012 IEEE International Reliability Physics Symposium (IRPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130428119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Copper electromigration failure times evaluated over a wide range of voiding phases 铜电迁移失效时间评估在大范围的空化相
2012 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2012-04-15 DOI: 10.1109/IRPS.2012.6241894
Yunlong Li, K. Croes, T. Kirimura, Y. Siew, Z. Tokei
{"title":"Copper electromigration failure times evaluated over a wide range of voiding phases","authors":"Yunlong Li, K. Croes, T. Kirimura, Y. Siew, Z. Tokei","doi":"10.1109/IRPS.2012.6241894","DOIUrl":"https://doi.org/10.1109/IRPS.2012.6241894","url":null,"abstract":"Electromigration failure times of 100 nm wide dual damascene Cu interconnects have been evaluated over a very wide range of different stages of void formation and growth. Voids that did not span the whole line width and height have been monitored using the so-called local sense structures, while standard single via structures were used to study fully grown voids. The activation energy Ea did not change over the whole experimental range of failure times indicating that the main diffusion path during void formation and growth does not change in our semi-bamboo lines. The earlier reported increase in distributional spread σ after full void formation is less pronounced during void formation which is due to different kinetics before and after full void formation. The use of defining failure criteria before full void formation has been explored as a tool to reduce electromigration test times. Due to the constant Ea, test times can be reduced by over a factor of two.","PeriodicalId":341663,"journal":{"name":"2012 IEEE International Reliability Physics Symposium (IRPS)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116559993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Engineering optimal high current characteristics of high voltage DENMOS 工程高电压DENMOS的最佳大电流特性
2012 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2012-04-15 DOI: 10.1109/IRPS.2012.6241819
A. Salman, F. Farbiz, A. Appaswamy, H. Kunz, G. Boselli, M. Dissegna
{"title":"Engineering optimal high current characteristics of high voltage DENMOS","authors":"A. Salman, F. Farbiz, A. Appaswamy, H. Kunz, G. Boselli, M. Dissegna","doi":"10.1109/IRPS.2012.6241819","DOIUrl":"https://doi.org/10.1109/IRPS.2012.6241819","url":null,"abstract":"This paper demonstrates the dramatic improvement in ESD performance of HV DENMOS and LDMOS obtained by using selective drain extension silicide blocking (SBLK). The results are validated through 3D TCAD and TLP measurements on different technologies. Measured D.C. Id-Vd characteristics show minimal performance impact due to the addition of SBLK region.","PeriodicalId":341663,"journal":{"name":"2012 IEEE International Reliability Physics Symposium (IRPS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122187590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Abnormal ESD failure mode with low-voltage turn-on phenomenon of LDMOS output driver LDMOS输出驱动器具有低压导通现象的异常ESD失效模式
2012 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2012-04-15 DOI: 10.1109/IRPS.2012.6241891
Jaeyoung Park, M. Orshansky
{"title":"Abnormal ESD failure mode with low-voltage turn-on phenomenon of LDMOS output driver","authors":"Jaeyoung Park, M. Orshansky","doi":"10.1109/IRPS.2012.6241891","DOIUrl":"https://doi.org/10.1109/IRPS.2012.6241891","url":null,"abstract":"An abnormal ESD failure mode caused by a low-voltage turn-on phenomenon in an LDMOS is found on a DC-DC converter chip. Experimental investigation has shown that gate-coupling is the root cause of such low-voltage turn-on behavior. To prevent this behavior, a novel gate turn-off circuit is proposed. The solution is effective: the test chip measurements show an increase in HBM values from 1500 V to 4000 V.","PeriodicalId":341663,"journal":{"name":"2012 IEEE International Reliability Physics Symposium (IRPS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122222956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Volcano effect in open through silicon via (TSV) technology 开孔硅孔(TSV)技术中的火山效应
2012 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2012-04-15 DOI: 10.1109/IRPS.2012.6241924
J. Kraft, E. Stuckler, C. Cassidy, W. Niko, F. Schrank, E. Wachmann, C. Gspan, F. Hofer
{"title":"Volcano effect in open through silicon via (TSV) technology","authors":"J. Kraft, E. Stuckler, C. Cassidy, W. Niko, F. Schrank, E. Wachmann, C. Gspan, F. Hofer","doi":"10.1109/IRPS.2012.6241924","DOIUrl":"https://doi.org/10.1109/IRPS.2012.6241924","url":null,"abstract":"Through Silicon Via (TSV) technology, to serve as electrical connection between metallization layers on the front and backside of the same wafer, has been developed by austriamicrosystems AG. During the development phase, defects were found that could be assigned to an established defect type known as “contact liner volcano”. To our knowledge this is the first time that such a volcano formation is reported from the inside of a TSV.","PeriodicalId":341663,"journal":{"name":"2012 IEEE International Reliability Physics Symposium (IRPS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122264770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Back-end dielectrics reliability under unipolar and bipolar AC-stress 后端电介质在单极和双极交流应力下的可靠性
2012 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2012-04-15 DOI: 10.1109/IRPS.2012.6241804
E. Chery, X. Federspiel, G. Beylier, C. Besset, D. Roy, F. Volpi, J. Chaix
{"title":"Back-end dielectrics reliability under unipolar and bipolar AC-stress","authors":"E. Chery, X. Federspiel, G. Beylier, C. Besset, D. Roy, F. Volpi, J. Chaix","doi":"10.1109/IRPS.2012.6241804","DOIUrl":"https://doi.org/10.1109/IRPS.2012.6241804","url":null,"abstract":"The present paper compares the effects of AC and DC electrical stress on low-κ SiOCH and high-κ ZrO2 and Ta2O5 back-end dielectrics. A wide panel of stress conditions has been assessed, mixing DC, unipolar/bipolar and relaxation times. The DC-stress being the reference stress condition, no enhancement of the time-to-breakdown (TBD) has been found with pure bipolar stress. On the contrary unipolar stress showed a strong improvement of this characteristic. We propose that the lifetime enhancement is due to a charge detrapping mechanism within the dielectric that affects the defect density. Under unipolar- and relax-bipolar-stress the time-to-breakdown has been corrected by the duty cycle in order to consider the effective duration of the stress. In this study no impact of copper has been found on the breakdown behaviour.","PeriodicalId":341663,"journal":{"name":"2012 IEEE International Reliability Physics Symposium (IRPS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123118364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
TSV defects and TSV-induced circuit failures: The third dimension in test and design-for-test TSV缺陷和TSV引起的电路故障:测试和为测试而设计的第三维度
2012 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2012-04-15 DOI: 10.1109/IRPS.2012.6241859
K. Chakrabarty, Sergej Deutsch, Himanshu Thapliyal, Fangming Ye
{"title":"TSV defects and TSV-induced circuit failures: The third dimension in test and design-for-test","authors":"K. Chakrabarty, Sergej Deutsch, Himanshu Thapliyal, Fangming Ye","doi":"10.1109/IRPS.2012.6241859","DOIUrl":"https://doi.org/10.1109/IRPS.2012.6241859","url":null,"abstract":"3D integrated circuits (3D ICs) based on through-silicon vias (TSVs) have emerged as a promising solution for overcoming interconnect and power bottlenecks in IC design. However, testing of 3D ICs remains a significant challenge, and breakthroughs in test technology are needed to make 3D integration commercially viable. This paper first presents an overview of TSV-related defects and the impact of TSVs in the form of new defects in devices and interconnects. The paper next describes recent advances in testing, diagnosis, and design-for-testability for 3D ICs and techniques for defect tolerance using redundancy and repair. Topics covered include various types of TSV defects, stress-induced mobility and threshold-voltage variation in devices, stress-induced electromigration in inter-connects, pre-bond and test-bond testing (including TSV probing), and optimization techniques for defect tolerance.","PeriodicalId":341663,"journal":{"name":"2012 IEEE International Reliability Physics Symposium (IRPS)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133941675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 62
The impact of melting during reset operation on the reliability of phase change memory 复位过程中熔化对相变存储器可靠性的影响
2012 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2012-04-15 DOI: 10.1109/IRPS.2012.6241872
P. Du, Jau-Yi Wu, T. Hsu, Ming-Hsiu Lee, Tien-Yen Wang, Huai-Yu Cheng, E. Lai, S. Lai, H. Lung, Sangbum Kim, M. BrightSky, Yu Zhu, S. Mittal, R. Cheek, S. Raoux, E. Joseph, A. Schrott, Jing Li, C. Lam
{"title":"The impact of melting during reset operation on the reliability of phase change memory","authors":"P. Du, Jau-Yi Wu, T. Hsu, Ming-Hsiu Lee, Tien-Yen Wang, Huai-Yu Cheng, E. Lai, S. Lai, H. Lung, Sangbum Kim, M. BrightSky, Yu Zhu, S. Mittal, R. Cheek, S. Raoux, E. Joseph, A. Schrott, Jing Li, C. Lam","doi":"10.1109/IRPS.2012.6241872","DOIUrl":"https://doi.org/10.1109/IRPS.2012.6241872","url":null,"abstract":"Operation impact on endurance performance in GST-based phase change memory is investigated from small arrays to large test chips. SET operation induced electromigration and phase segregation are observed. For the first time, the RESET melting healing effect is proposed to partially repair the SET induced damage and further extend the endurance. This concept can be easily implemented by accordingly designing the control circuits.","PeriodicalId":341663,"journal":{"name":"2012 IEEE International Reliability Physics Symposium (IRPS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134463715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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