27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium最新文献

{"title":"Tape based CSP package supports fine pitch wirebonding","authors":"J. Geissinger, F. Keller, S. Treviño, T. Kamei","doi":"10.1109/IEMT.2002.1032720","DOIUrl":"https://doi.org/10.1109/IEMT.2002.1032720","url":null,"abstract":"Utilizing the existing wire bonding infrastructure, it is now possible to extend wire bonding, substrate, and molding technologies to produce extremely low cost, fine pitch CSP package solutions. These packages exploit available 35/spl mu/m die pad pitch capability and 20/20/spl mu/m line/space tape substrate technology to produce low-cost, miniature, light-weight devices at a maximum mounted thickness of 0.8mm (to comply with JEDEC outline for wfBGA). These types of CSP solutions are required in portable handheld devices with increased functionality, such as cell phones, pagers, personal digital assistants (PDAs), digital cameras, and gaming devices. 3M, Sumitomo Bakelite, and Kulicke & Soffa have collaborated in the design, manufacture, and validation of a 10mm /spl times/ 10mm flex circuit based BGA device at 0.5mm ball pitch and 276 I/Os. The key to this package is the use of an on-die in-line bond pad pitch of 35/spl mu/m and an on-substrate staggered bond pad design with an effective pitch of 50/spl mu/m. This substrate technology enables the ultimate in low cost packaging due to the small die size and resulting package size.","PeriodicalId":340284,"journal":{"name":"27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116804398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Cost and manufacturing optimization of high performance communication hardware using a daughter module","authors":"S. Camerlo, S. Priore, M. Brillhart, W. Cheng, Lekhanh Dang, J. Chen","doi":"10.1109/IEMT.2002.1032736","DOIUrl":"https://doi.org/10.1109/IEMT.2002.1032736","url":null,"abstract":"The radical rise in localized component density has forced designers to utilize extremely high density, high layer count printed circuit boards. These high layer counts make the board more difficult, and more expensive to fabricate, resulting in higher costs, reduced raw board yield and a restricted supply base of PCB shops that can build the required substrates. In many instances the need for multiple layer counts is usually limited to a small percentage of the total PCB surface area where a high I/O ASIC and its associated memory are located. To overcome these limitations, the option of removing the complex, localized, high-density routing area(s) of the circuitry and moving it to a daughter module was employed to achieve a lower cost PCB and expanded PCB supply base.","PeriodicalId":340284,"journal":{"name":"27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121661153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Material and process considerations for reliable overniolded flip chip PBGAs","authors":"H. Chan, S. Álvarez, G. Carson","doi":"10.1109/IEMT.2002.1032717","DOIUrl":"https://doi.org/10.1109/IEMT.2002.1032717","url":null,"abstract":"Recently a p a t deal of interest has arisen in the overmolding of flip chip assemblies. Reasons v q from perceived reliabiliv advantages to easier handling of thin substrates to aesthetic impressions on the final customer (making a flip chip BGA look like a wirebonded BGA). Fabricating these assemblies, in its simplest form, producing a conventional underfilled flip chip PBGG then encapsulating the entire die and surrounding substrate with a thermosetting resin by a transfer moldmg process. The appearance of such a package and its handling characteristics are practically the same as that of a wirebonded BGA. The usual unddill materials and processes are commonly employed in fabricating the underfilled assemblies, however, the imposition of a relatively constraining mold compound provides the opportunity to explore options not available to conventional flip chip PBGAs, such as very soft undedills or unfilled, fluxing underlills. These experiments attempted to define material and process l i tat ions required in assembling a package capable of JEDEC 3 (22OOC) followed by subsequent thermal cycling or autoclave testing. Assembly processes are described in detail. Reliability results are compared with those of non-molded assemblies. Success was gauged by the extent of cracking and/or delamination within the packages. Failure modes are discussed and related to underfill physical properties. Introdllction Demands for speedy and low cost packages are driving the packaging industry toward flip chip at a t e d i c rate. This once exotic packaging scheme is now being adopted industrywide as a viable, cost-effective alternative to wire bonded packages, especially for CSPs. In particular, components for portable communications and power conversion devices benefit from ilip chip technology.’ The new package must, however, adapt to existing requirements for form factor, appearance, and parts handling. That is difficult for conventional flip chip packages. They look quite Merent. The die and underfa, whose appearance may vary significantly from package to package, are o h subjected to appearance criteria unlike those of molded packages. Handling may be problematic as well, since vision and placement equipment ofien must be reconfigured to deal with the backside of the packaged die rather than the matte finish of a molded package. Damage to the die backside is commonly a concern among those handling and placing flip chip packages. For all of these reasons the switch to flip chip is more seamless if the package looks like the package that it’s replacing (often a molded array package). Molding over the die of a flip chip package removes many of the handling and appearance issues normally encountered in inboducing flip clup packaging. Mold compound gives the package a uniform, familiar appearance and M e n s the structure of the package. StSening is especially practical where very thin substrates are employed. Figure 1 shows some of the features of a so-called arr","PeriodicalId":340284,"journal":{"name":"27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133845086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Automatic wedge bonding with ribbon wire for high frequency applications","authors":"I. Qin, P. Reid, R. Werner, D. Doerr","doi":"10.1109/IEMT.2002.1032732","DOIUrl":"https://doi.org/10.1109/IEMT.2002.1032732","url":null,"abstract":"Wedge bonded ribbon wire has demonstrated the ability to provide better performance than round wire in many high performance devices. The commercial marketplace for microwave and optical devices that operate at very high frequency has grown to the extent that high quality, high volume ribbon wire bonding processes have become a necessity. When a high frequency electrical signal is carried on a wire, the signal travels along the thin layer near the surface. This is called the skin effect. Due to the skin effect, the same cross section ribbon wire has much higher current carrying capability than round wire. Ribbon wire also has smaller effective inductance and less signal cross talk than round wire. In addition to superior electrical attributes, ribbon wire also provides wire bonding process benefits, such as very low loops and better looping control due its resistance to sway and sagging. The bond force required to bond ribbons is much lower than that for round wire because, in a sense, the ribbon is pre-deformed so the geometry of its contact area more closely matches that of the device surface. This paper reviews the many performance benefits ribbon wire can provide, and examines the market and process requirements of ribbon wire bonding. It shows how optimal bonding results are achieved through process optimization and Design of Experiments (DOE) and reviews typical bonding and assembly challenges for common high-frequency packages. Test methodologies to identify the optimal wedge bonding tool configuration and ribbon composition also are summarized, including DOE and statistical analyses for fine ribbon wires [13 pm x 51 pm (0.5 x 2 mil)] and heavy ribbon wires [25.4 μm x 254 μm (1 x 10 mil)]. Results from these tests are presented as guidelines for determining process capability in production applications.","PeriodicalId":340284,"journal":{"name":"27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131098534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effect of underfill staging time on fillet depression","authors":"Y. W. Cheong, E. Then, Cheong Huat Ng, G. S. Lee, M. Diaz, G. De Guia, Mon Leong Loke","doi":"10.1109/IEMT.2002.1032731","DOIUrl":"https://doi.org/10.1109/IEMT.2002.1032731","url":null,"abstract":"Underfill is a material typically used in flip-chip technology to provide a mechanical bonding between the die and the substrate. During the recent development of a new FC-BGA package, one of the main challenge was the selection of a single dispense underfill with a self-filleting capability. In the course of the evaluation a new fillet defect was encountered. The defect resulted in a yield loss of approximately 30% at the post epoxy visual inspection. However, upon closer inspection, what appears initially as a crack was later found out through FA cross sectioned results to be a deep groove running parallel to the edge of the die, a short distance away from the die edge. The defect was consequently referred to as Fillet depression. There were also micro depressions that were visible only under a microscope at 40x magnification. Closer inspection showed these micro depressions have resin rich tips. From the commonality study conducted the additional staging time for the underfill was determined to be the dominant factor that cause fillet depression. This paper includes a detail description of the new defect and a hypothesis for the effect of staging time on the filleting quality.","PeriodicalId":340284,"journal":{"name":"27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131307277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reliability of CSP/lead free solder joints with different surface finishes and reflow profiles","authors":"D. Me, D. Geiger, M. Arra, D. Shangguan, H. Phan","doi":"10.1109/IEMT.2002.1032773","DOIUrl":"https://doi.org/10.1109/IEMT.2002.1032773","url":null,"abstract":"The reliability of chip scale package (CSP) using lead free solder process was studied in this paper. The impact of reflow process, peak reflow temperature ranging from Tm+5'C to Tm+40\"C (Tmmelting temperature of the lead free) and the dwell time ranging from 30 to 90s were investigaged. Two commonly used PCB surface finishes were employed organic solderability preservative (OSP) and electronic nickel immersion gold (ENIG). The test vehicle covers various CSPs including rigid interpose, laminate interpose and land grid array. From the results of thermal cycling test, it is learnt that all CSPs tested are qualified for consumer products application but only CSP24 and CSP308 can meet the requirement of telecomm applications. Compared to ENIG, OSP is more reliable as PCB surface finish in both thermal cycling and thermal shock tests. The reliability is affected not only by the peak temperature but also by the dwell time. The optimum setting would be different when using ENIG or OSP finishes.","PeriodicalId":340284,"journal":{"name":"27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125915178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Equivalent driver model for fast system simulation","authors":"Jun’e Feng, Ching-Chao Huang","doi":"10.1109/IEMT.2002.1032765","DOIUrl":"https://doi.org/10.1109/IEMT.2002.1032765","url":null,"abstract":"As the clock speed increases and rise time decreases, an accurate I/O driver model is crucial for robust system designs. Due to the runtime limitations, a full-blown driver circuit model is impractical for those designs that require numerous simulation runs. Take the high-speed Rambus memory channel design as an example. Thousands of data read and data write simulations were performed with various patterns, configurations, and comer models. Many complex interconnect models are included in the simulation decks, in the form of frequency-dependent, lossy, and coupled transmission lines [1]. The only nonlinear model that is present is either the memory controller circuitry for data write or RDRAM driver circuitry for data read simulations. This paper describes a reduced, but equivalent, RDRAM driver model that significantly speeds up the simulation time for Rambus memory channel designs. The concept of using a reduced model in place of a full-circuit model is not new [2]. This paper, however, chooses a model that consists of a simple level-1 transistor in parallel with a voltage-controlled current source. A systematic approach is shown that curvefits the I-V curve by a level-1 transistor and matches the load line by a current source. The reduced model thus obtained results in time-domain waveforms that are nearly identical to the full-circuit's. Finally, it is noted that the same procedures can be applied to derive reduced models for many nonlinear circuits.","PeriodicalId":340284,"journal":{"name":"27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132283166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design and characterization of a high-performance wire-bond ball-grid-array package","authors":"Ching-Chao Huang, D. Secker, Ling Yang, Jun Feng, N. Jain","doi":"10.1109/IEMT.2002.1032762","DOIUrl":"https://doi.org/10.1109/IEMT.2002.1032762","url":null,"abstract":"The wire-bond ball-grid-array (BGA) package is of interest because of its low cost and high pin counts. For better electrical performance, the coupling in the wire-bond regions needs to be contained. This paper shows a double-swizzle design that reduces coupling by ∼40% from a reference single-swizzle design. The smaller coupling was achieved through the proper assignment of ground wires. Test packages with shorted load were built, and the measurements were done by connecting either a vector network analyzer (VNA) or a time-domain reflectometer (TDR) to the balls of the package. The coupled models of bond wires, fanouts, traces, and plating stubs were then extracted from the measured data by a customized extractor. The extracted models gave some insights into the package. The attenuation was larger than expected. Some spikes in the measured S11 plots were attributed to the coupling. A package model without coupling would not be able to capture these spikes. Yet there were other spikes that were unexplained. They were finally tracked down to be caused by the Vdd plane and routing. Connecting decoupling capacitors between Vdd and ground balls moved the resonance spikes to higher frequencies. Shorting the Vdd and ground balls eliminated these mysterious spikes altogether.","PeriodicalId":340284,"journal":{"name":"27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126815675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Flux-underfill compatibility and failure mode analysis in high yield flip chip processing","authors":"P. Houston, D. Baldwin, W. Tsai","doi":"10.1109/IEMT.2002.1032727","DOIUrl":"https://doi.org/10.1109/IEMT.2002.1032727","url":null,"abstract":"The compatibility of flux and underfill material systems significantly contributes to the formation and growth of process-induced defects and further influences flip chip reliability. Various no-clean fluxes, along with a water-soluble flux used as the baseline, are tested with two fast flow, snap cure underfills. Liquid-to-liquid thermal shock and temperature and humidity tests are conducted to evaluate the reliability of each flux-underfill material system. The failure modes, specifically underfill delamination, solder fatigue, and die cracking, are identified and analyzed. The correlation among process manufacturing defects, failure modes, and long-term reliability are determined. Understanding these failure modes will further enable and facilitate the implementation of low cost, high yield flip chip processing in standard surface mount technology.","PeriodicalId":340284,"journal":{"name":"27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126170609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Environmentally friendly, high thermal resistant, low CTE substrate material for semiconductor packaging","authors":"T. Baba","doi":"10.1109/IEMT.2002.1032785","DOIUrl":"https://doi.org/10.1109/IEMT.2002.1032785","url":null,"abstract":"Semiconductor packaging technology has been moving towards increased miniaturization, lighter weight and higher density. Flip Chip packaging is therefore becoming the mainstream packaging technology for next generation devices. The technology trend has been moving towards much finer pitch interconnections between the semiconductor chip and the package substrate, much narrower circuit width on the substrate and a much smaller diameter of the circuitry layer interconnection. Thus, concerns arise regarding mechanical and electrical deterioration and failure at the interconnections. Previously much more focus had been placed on systems utilizing Halogen-free and Pb-free raw materials in order to meet environmental requirements. In this paper, we are reporting a new substrate material for semiconductor packages (Copper-clad-laminate: ELC-4785GS, Prepreg: EI-6785GS, Build-up material: APL-4601) which Sumitomo Bakelite has begun developing.","PeriodicalId":340284,"journal":{"name":"27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128927968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}