27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium最新文献_第6页

Electrical modeling and analysis of lead-bonded and wire-bonded /spl mu/BGA/sup /spl reg// packages for high-speed memory applications 用于高速存储器应用的铅键和线键/spl mu/BGA/sup /spl reg//封装的电气建模和分析

27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium Pub Date : 2002-11-07 DOI: 10.1109/IEMT.2002.1032763

Byongsu Seol, L. Pflughaupt

引用次数: 4

Pressfit technology for 3-D molded interconnect devices (MID) - A lead-free alternative to solder joints - challenges and solutions concepts 用于3-D模压互连器件(MID)的Pressfit技术-焊点的无铅替代品-挑战和解决方案概念

27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium Pub Date : 2002-11-07 DOI: 10.1109/IEMT.2002.1032761

M. Eisenbarth, K. Feldmann

{"title":"Pressfit technology for 3-D molded interconnect devices (MID) - A lead-free alternative to solder joints - challenges and solutions concepts","authors":"M. Eisenbarth, K. Feldmann","doi":"10.1109/IEMT.2002.1032761","DOIUrl":"https://doi.org/10.1109/IEMT.2002.1032761","url":null,"abstract":"The continuous trend in electronics production towards new substrate materials, the development of the third dimension by molded interconnect devices (3-D MID) and the constantly rising integration of functions and miniaturization of electronic products leads to new challenges for interconnection technology. Compared to interconnections established by solder materials the pressfit technology offers many advantages. Most important is that no temperature is needed which results in a thermal stress-free situation for the base substrate. Seen from the ecological side, no fumes, gases or cleaning fluids which may reduce the contact reliability of the connector come into existence. This kind of interconnection is also completely lead-free due to the fact that no lead containing solders are needed. Also undesirable effects like cold solder joints, bridges or opens do not occur. And finally, recycling of connectors can be made easily by disassembly of connector and base material. This paper shows, how these advantages can be made accessible for 3-D MID-Technology, too. The thermoplastic base materials covered within this project are: PC/ABS-Blend, Polyamide 66, Polyetherimide and Liquid Crystal Polymer (reference: standard FR-4). With this four different substrates almost the whole field of thermoplastics can be covered (commodity, technical and high temperature materials). Based on a test vehicle with various hole diameters and forms it is the aim to show the best combinations between hole diameter, used compliant press-fit connector (four pins with different geometries) and type of thermoplastic base material. The main intention of the investigations described in this paper is to make pressfit technology be useable for molded interconnect devices.","PeriodicalId":340284,"journal":{"name":"27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium","volume":"05 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128886641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Co-simulation of dynamic compact models of packages with the detailed models of printed circuit boards 封装动态紧凑模型与印刷电路板详细模型的联合仿真

27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium Pub Date : 2002-11-07 DOI: 10.1109/IEMT.2002.1032768

M. Rencz, V. Székely, A. Poppe, B. Courtois

引用次数: 5

Finite element based solder joint fatigue life predictions for a same die size-stacked-chip scale-ball grid array package 基于有限元的相同晶片尺寸-积片-球栅阵列封装焊点疲劳寿命预测

27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium Pub Date : 2002-11-07 DOI: 10.1109/IEMT.2002.1032767

B. Zahn

引用次数: 79

Addressing emerging test challenges for multilevel signaling devices 解决多电平信令设备新出现的测试挑战

27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium Pub Date : 2002-11-07 DOI: 10.1109/IEMT.2002.1032782

G. Schroeder

{"title":"Addressing emerging test challenges for multilevel signaling devices","authors":"G. Schroeder","doi":"10.1109/IEMT.2002.1032782","DOIUrl":"https://doi.org/10.1109/IEMT.2002.1032782","url":null,"abstract":"Multilevel analog signaling techniques are rapidly gaining favor for their ability to provide very high-speed symbol transfer rates at appreciably lower observed line rates. Early bipolar methods such as Alternate Mark Inversion have paved the way to signaling techniques using four or more levels. In light of rapidly growing interest in multimedia communications, a particularly important application of multilevel signaling methods is Gigabit Ethernet (1000Base-T), which combines Five-level Pulse Amplitude Modulation (PAM5) with the use of parallel differential. signal lines to increase symbol rates while retaining low line rates. For device manufacturers, however, multilevel signaling poses new challenges for achieving reliable, high-throughput testing needed to deliver required levels of quality and production volume. Documented in IEEE Std 802.3ab-1999, the IEEE offers recommendations for several tests for 1000Base-T PHY devices to ensure signal integrity, timing and functional performance. Among these recommendations, specific test scenarios address the need for measurements of a range of amplitude, voltage, distortion, timing, jitter and functional characteristics. In turn, the measurement of these characteristics in multilevel signaling devices carries specific implications for signal generation and measurement. Very high frequency arbitrary waveform generators (AWGs) win be needed to address higher bandwidth signals across multiple independent differential channels used in applications such as Gigabit Ethernet. Similarly, integrated timing digitizers will be needed to complete time measurements including single-shot propagation delay (Tpd), jitter and frequency. By anticipating these and other emerging test challenges associated with multilevel signaling, device manufacturers will be able to avoid potential delays in production test and speed delivery of devices for this evolving market segment.","PeriodicalId":340284,"journal":{"name":"27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131274865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

cLGA/spl reg/ sockets: qualification, production, and performance ready cLGA/spl reg/ sockets:资格，生产和性能准备

27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium Pub Date : 2002-11-07 DOI: 10.1109/IEMT.2002.1032734

D. Neidich

引用次数: 1

The use of pre-molded leadframe cavity package technologies in photonic and RF applications 在光子和射频应用中使用预模引线框架腔封装技术

27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium Pub Date : 2002-11-07 DOI: 10.1109/IEMT.2002.1032777

A. Longford, B. Radloff

引用次数: 3

Optimization of nanocomposite integral capacitor fabrication using neural networks and genetic algorithms 基于神经网络和遗传算法的纳米复合材料集成电容器制造优化

27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium Pub Date : 2002-11-07 DOI: 10.1109/IEMT.2002.1032737

T. Thongvigitmanee, Gary S. May

{"title":"Optimization of nanocomposite integral capacitor fabrication using neural networks and genetic algorithms","authors":"T. Thongvigitmanee, Gary S. May","doi":"10.1109/IEMT.2002.1032737","DOIUrl":"https://doi.org/10.1109/IEMT.2002.1032737","url":null,"abstract":"Thin film integral capacitors using polymer-ceramic composites have been developed for next-generation electronic packaging applications. To achieve a high dielectric constant, bimodal ceramic particle distributions, along with particles modified by a surfactant and mixed ultrasonically with the polymer have been explored. This paper presents a statistically designed experiment for systematic characterization of the dielectric constant and loss tangent of integral capacitors formed in this manner by using barium titanate particles in an epoxy polymer dielectric. We determine these quantities as a function of the particle size of the ceramic, the volume fraction of ceramic in the polymer matrix, the polymer cure time, the polymer cure temperature, the percent of surfactant, the ultrasonic mixing time, and the ball milling time for ceramic surface modification. These factors are examined by means of a partial factorial experiment requiring 32 runs. Further experimentation is performed to generate sufficient data for process modeling. To develop such models, we train neural networks to model the variation as a function of input variables using the experimental data. These models are then used for process optimization using genetic algorithms. Using this methodology, we determine the proper combination of polymer/ceramic materials and process conditions to achieve desirable electrical properties.","PeriodicalId":340284,"journal":{"name":"27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132384943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Processing and reliability of flip chip with lead-free solders on halogen-free microvia substrates 无卤素微孔基板上无铅焊料倒装芯片的加工和可靠性

27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium Pub Date : 2002-11-07 DOI: 10.1109/IEMT.2002.1032771

D. Baldwin, G. Baynham, K. Boustedt, C. Wennerholm

{"title":"Processing and reliability of flip chip with lead-free solders on halogen-free microvia substrates","authors":"D. Baldwin, G. Baynham, K. Boustedt, C. Wennerholm","doi":"10.1109/IEMT.2002.1032771","DOIUrl":"https://doi.org/10.1109/IEMT.2002.1032771","url":null,"abstract":"An assembly process for environmentally conscious low cost flip chip assembly to microvia laminate substrates is presented, based on a fully integrated high speed flip chip assembly line. The process includes the flux application, chip placement, reflow process, and underfill processing. Flux and underfill material compatibility is discussed, and data presented analyzing the quality of the solder joint formation and underfill adhesion to halogen-free solder masks. 204-/spl mu/m pitch peripheral bump, daisy chain test chips with edge lengths of 5 mm and 10 mm respectively are used. Comprehensive reliability results, are presented, comparing the two lead-free to tin/lead eutectic interconnect systems. The chips are assembled on microvia substrates with electroless nickel/immersion gold surface finish, comparing conventional to halogen-free FR-4 and solder masks. A fast flow snap cure underfill, qualified for use with eutectic tin/lead joints on conventional FR-4, is used for both board types. Reliability results from air-to-air thermal shock testing are presented, comparing lead-free to eutectic interconnect systems mounted on conventional and halogen-free microvia substrates. Process and failure mode analysis are presented, based on X-ray inspection, C-SAM analysis, and assembly cross sections.","PeriodicalId":340284,"journal":{"name":"27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125301270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Solder bumping via paste reflow for area array packages 通过区域阵列封装的膏体回流来碰撞焊料

27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium Pub Date : 2002-11-07 DOI: 10.1109/IEMT.2002.1032715

Benlib Huang, N. Lee

引用次数: 15