27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium最新文献_第5页

Requirement specifications for an enterprise level collaborative, data collection, quality management and manufacturing tool for an EMS provider EMS供应商的企业级协作、数据收集、质量管理和制造工具的需求规范

27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium Pub Date : 2002-11-07 DOI: 10.1109/IEMT.2002.1032741

S. Bahl, R. Venkatesh, J. Craik, R. Bedi, H. Uriarte, K. Srihari

{"title":"Requirement specifications for an enterprise level collaborative, data collection, quality management and manufacturing tool for an EMS provider","authors":"S. Bahl, R. Venkatesh, J. Craik, R. Bedi, H. Uriarte, K. Srihari","doi":"10.1109/IEMT.2002.1032741","DOIUrl":"https://doi.org/10.1109/IEMT.2002.1032741","url":null,"abstract":"Numerous software applications that serve as effective tools in solving localized issues for an electronics manufacturing service (EMS) provider are currently available. However, there are very few products available in the market for an EMS provider that offer an integrated solution to issues ranging from the production floor to supplier quality. Applications with features including that of manufacturing execution systems (MES) and shop floor control systems would be examples of middle layer systems. This paper discusses the requirement specifications developed for a middle layer software tool to support collaborative manufacturing, extend shop floor visibility, monitor product yield and defects, and improve unit level traceability. Also, the software tool would assist in increasing operational efficiency by reducing paperwork of shop floor personnel, helping to locate reference designators and finding part numbers, and reducing debug time. The application interfaces with SMT, tests and inspection equipment for effective product and process monitoring. This paper also discusses the issues that are of concern to quality department personnel and customers such as the non-conformance materials report (NCMR) and tracking of corrective action requests associated with them and providing root cause analysis capability for NCMRs. The requirement specifications detailed here were developed to meet the needs of both high and low volume facilities involved in PCB assembly and subsequent box-build activities. This paper delineates the functionality required in an integrated system at an EMS provider for it to be an effective tool for manufacturing, improving quality and integrating data from facilities worldwide.","PeriodicalId":340284,"journal":{"name":"27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115817432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Wafer level underfill - processing and reliability 晶圆级底填处理和可靠性

27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium Pub Date : 2002-11-07 DOI: 10.1109/IEMT.2002.1032723

L. Nguyen, H. Nguyen, A. Negasi, Q. Tong, S. Hong

{"title":"Wafer level underfill - processing and reliability","authors":"L. Nguyen, H. Nguyen, A. Negasi, Q. Tong, S. Hong","doi":"10.1109/IEMT.2002.1032723","DOIUrl":"https://doi.org/10.1109/IEMT.2002.1032723","url":null,"abstract":"Underfill materials play a major role in the reliability of flip chip packages. These adhesives have been the subject of much research and development in the last few years, and improvement in material performance has been obtained. However, the assembly method still remains unchanged, with the underfill being dispensed at the individual die level after flip chip reflow. Even with the arrival of \"no-flow\" underfills, assembly still requires depositing the underfill material onto the flip chip site prior to positioning the flip chip die. Processing underfill at the wafer level brings in a new paradigm shift to the area of flip chip packaging. Precoating the wafer with the underfill. will create significant savings in both time and money. The application cycle time of the wafer level process becomes equivalent to one single dispensing operation. This paper will present and discuss the latest results obtained with stencil printing used as the application method for the wafer level process. Several experimental underfill formulations were tested as a function of various printing conditions. With the optimal process conditions, the desired coating thickness can be applied without damage to bumped wafers. Assembly challenges together with reliability data are presented.","PeriodicalId":340284,"journal":{"name":"27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115188668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Lead-free low-cost flip-chip process chain: layout, process, reliability 无铅低成本倒装芯片工艺链:布局、工艺、可靠性

27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium Pub Date : 2002-11-07 DOI: 10.1109/IEMT.2002.1032718

P. Woflick, K. Feldmann

{"title":"Lead-free low-cost flip-chip process chain: layout, process, reliability","authors":"P. Woflick, K. Feldmann","doi":"10.1109/IEMT.2002.1032718","DOIUrl":"https://doi.org/10.1109/IEMT.2002.1032718","url":null,"abstract":"The ultimate way for miniaturization is the usage of flip-chip components. Instead of using costly ceramic PCBs, the use of standard FR-4 substrates offers a wide field for reducing costs. Together with the usage of stencil printing, this leads to a low-cost production chain. By using standard materials and processes, the flip-chips can be integrated in the existing SMT-production line. As the use of environmentally friendly lead-free solder alloys has until now not been tested in detail, the processing and reliability still need to be analyzed. This paper aims to show an overview of the lead-free low-cost flip-chip process chain, starting with a suitable layout of the pads and solder resist openings of the substrate and the openings of the stencil. The influence of the process parameters for solder paste printing is shown. The difficulties of placement of flip-chips are discussed. Possible reflow soldering methods are laid down and the aspects of using nitrogen-atmosphere are also taken into account. Additionally, this paper explains the great importance of the underfill process, points out the possible ways of inspecting flip-chip connections and takes a look at the long-term reliability of flip-chip solder joints. As an outlook a basic approach for selective flip-chip soldering is given.","PeriodicalId":340284,"journal":{"name":"27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128661246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

A structured approach to lead-free IC assembly transitioning 一种无铅集成电路组装过渡的结构化方法

27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium Pub Date : 2002-11-07 DOI: 10.1109/IEMT.2002.1032758

L. Nguyen, R. Walberg, Z. Lin, T. Koh, Y. Bong, M. C. Chua, S. Chuah, J. J. Yeoh

{"title":"A structured approach to lead-free IC assembly transitioning","authors":"L. Nguyen, R. Walberg, Z. Lin, T. Koh, Y. Bong, M. C. Chua, S. Chuah, J. J. Yeoh","doi":"10.1109/IEMT.2002.1032758","DOIUrl":"https://doi.org/10.1109/IEMT.2002.1032758","url":null,"abstract":"Market forces, trade restrictions, and customer perceptions rather than environmental realities have driven the lead-free movement. However, it cannot be turned around. Consequently, manufacturers, suppliers, and industry consortia have all been working towards a common acceptable drop-in replacement for the standard eutectic SnPb. Most U.S. and European groups support the use of SnAgCu alloys for surface mount applications. For instance, NEMI has recommended Sn3.9Ag0.6Cu as an industry standard for lead-free solder paste (with Sn0.7Cu for wave soldering), and is currently assessing its manufacturability and reliability. Similarly, SnAgCu alloys have been recommended for solder balls to be used in array packages. Unfortunately, there has been no recommendation for a lead-free finish for leaded packages, which still constitute the largest portion of the worldwide semiconductor packaging production. IC suppliers had to struggle to evaluate the various lead-free finish options available, and assess the resulting impact of the transition on their manufacturing logistics. This paper will provide the highlights of a structured program, at National Semiconductor Corp. to transition from SnPb to lead-free IC manufacturing.","PeriodicalId":340284,"journal":{"name":"27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122113459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Chip scale packaging techniques for RF SAW devices 射频SAW器件的芯片级封装技术

27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium Pub Date : 2002-11-07 DOI: 10.1109/IEMT.2002.1032724

M. Goetz, C. Jones

引用次数: 21

Removable tape using thermoplastic adhesive for QFN assembly process QFN装配过程中使用热塑性胶粘剂的可拆卸胶带

27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium Pub Date : 2002-11-07 DOI: 10.1109/IEMT.2002.1032750

Toshiya Kawai, Tomohiro Nagoya, Hidekazu Matsuura

{"title":"Removable tape using thermoplastic adhesive for QFN assembly process","authors":"Toshiya Kawai, Tomohiro Nagoya, Hidekazu Matsuura","doi":"10.1109/IEMT.2002.1032750","DOIUrl":"https://doi.org/10.1109/IEMT.2002.1032750","url":null,"abstract":"The miniaturization of IC packages is progressing rapidly with the increasing demand for mobile electronic equipment. In particular, the demand for the QFN (quad flat non-leaded package), a lead frame type CSP, is increasing now. The productivity of the QFN assembly process can become much higher by using the MAP (molded array packaging) technology. In that technology, QFN support tape is a key material. It needs not only to attach well to the backside of the lead frame to avoid flash burrs in molding, but also to be removed easily from the lead frame and the molding resin with no residue after molding. For this usage, we have developed a new thermoplastic adhesive by optimizing the chemical structure and the characteristics. The new thermoplastic adhesive has a high elastic modulus, low amount of outgassing, and enough adhesive strength at high temperatures. Therefore, our RT series QFN support tape reveals: (1) good wire bondability, (2) no flash burr in molding, and (3) no residue after removal. These tapes contribute more to high yield and high productivity in comparison with the conventional sticky adhesive tape in the QFN assembly process.","PeriodicalId":340284,"journal":{"name":"27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium","volume":"7 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132713460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Applications of intelligent control in improving dynamics of precision motion systems used in microelectronics manufacturing 智能控制在微电子制造业精密运动系统动力学改善中的应用

27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium Pub Date : 2002-11-07 DOI: 10.1109/IEMT.2002.1032790

Tian He

{"title":"Applications of intelligent control in improving dynamics of precision motion systems used in microelectronics manufacturing","authors":"Tian He","doi":"10.1109/IEMT.2002.1032790","DOIUrl":"https://doi.org/10.1109/IEMT.2002.1032790","url":null,"abstract":"Precision motion systems play a critical role in microelectronics manufacturing by accommodating different high precision and high speed requirements in all the fabrication, inspection, assembly, and handling processes. As the precision motion systems are subjected to greater acceleration, they become more sensitive to their high-frequency resonance, which is not a concern in low speed applications. Therefore better system dynamics are necessary for successful precision motion system design. A review is presented for intelligent control techniques applied to improve the dynamics of precision motion systems and their potential extension into microelectronics manufacturing. Based on the review, utilization of intelligent control technologies is proposed to suppress adverse system dynamic behaviors while requirements on system stiffness and tolerance can be significantly relaxed. This proposed strategy appears especially meaningful and attractive, given the reality that the control electronics of precision motion systems keeps getting more capability and less expensive and the control algorithms can be optimized and tested very quickly with little cost.","PeriodicalId":340284,"journal":{"name":"27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131251606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A study of solder paste release from small stencil apertures of different geometries with constant volumes 恒定体积下不同几何形状的钢板小孔释放锡膏的研究

27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium Pub Date : 2002-11-07 DOI: 10.1109/IEMT.2002.1032744

S. Aravamudhan, D. Santos, G. Pham-Van-diep, F. Andres

{"title":"A study of solder paste release from small stencil apertures of different geometries with constant volumes","authors":"S. Aravamudhan, D. Santos, G. Pham-Van-diep, F. Andres","doi":"10.1109/IEMT.2002.1032744","DOIUrl":"https://doi.org/10.1109/IEMT.2002.1032744","url":null,"abstract":"Stencil printing is a critical first step in surface mount assembly. It is often cited that about 50% or more of the defects found in the assembly of PCBs are attributed to stencil printing (R. Clouthier, 1997). Manufacturing techniques for the assembly of certain flip chips, chip scale packages and fine pitch ball grid arrays are testing the limits of current stencil printing capabilities. A thorough understanding of basic stencil printing principles would facilitate the design of printers, stencils and pastes, and would ultimately permit the extension of reliable print techniques to the very fine print arena. For small apertures, solder paste volume and consistency are critical to solder joint reliability. The work described in this paper examines the release performance of various solder pastes from a variety of aperture sizes and geometries. The focus of this study is a comparison of square versus circular apertures when the nominal volume of paste to be deposited is kept constant. This method of study is contrasted with published work wherein squares versus circles have been studied, but, in those, the dimensions (not volumes) were the same (e.g. 12 mil diameter circle as compared to a 12 mil on a side square aperture).","PeriodicalId":340284,"journal":{"name":"27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium","volume":"93 15","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131771082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

Characterisation of lead-free solder pastes for low cost flip-chip bumping 低成本倒装芯片碰撞用无铅焊膏的特性研究

27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium Pub Date : 2002-11-07 DOI: 10.1109/IEMT.2002.1032759

G. Jackson, R. Durairaj, Nduka Nnamdi (Ndy) Ekere

{"title":"Characterisation of lead-free solder pastes for low cost flip-chip bumping","authors":"G. Jackson, R. Durairaj, Nduka Nnamdi (Ndy) Ekere","doi":"10.1109/IEMT.2002.1032759","DOIUrl":"https://doi.org/10.1109/IEMT.2002.1032759","url":null,"abstract":"The need to implement high volume production for a Pb-free flip-chip assembly (unpackaged silicon die, with inputs/outputs I/Os at sub 100 /spl mu/m pitch) has raised interest within the electronics manufacturing industry to find reliable inexpensive manufacturing methods. One method currently being researched is wafer bumping using Pb-free solder paste stencil printing. The introduction of Pb-free materials is being driven by a European directive, Waste from Electronic and Electrical Equipment (WEEE), which necessitates the elimination of lead containing materials from electronics products by January 2008. This has put tremendous pressure on the electronics industry to find a suitable replacement for the widely used tin/lead based solder paste. One material already highlighted is the tin/silver/copper alloy. However, in order to successfully implement the new material into current manufacturing processes, an in-depth understanding of the materials properties is required; as little information is presently known. In this paper we evaluate the rheological properties of certain tin/silver/copper solder pastes currently being developed for low cost flip-chip wafer bumping. Rheological measurements provide useful data for understanding flow behaviour of solder pastes in the stencil printing process. Factors affecting the rheology of solder pastes are alloy type, particle size distribution (PSD), metal content and flux vehicle system. Removal of lead from the solder paste and developments in the flux to accommodate Pb-free materials will inherently affect the flow properties of the solder paste. Therefore, it is essential to the stencil printing process that these new lead-free materials are characterised in a rheological nature. This study, therefore, aims to understand the rheological behaviour of certain lead-free solder pastes for flip-chip assembly applications and to subsequently assist in new formulations replacing lead solders.","PeriodicalId":340284,"journal":{"name":"27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127320400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 17

A virtual prototyping test bed for electronics assembly 电子装配虚拟样机试验台

27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium Pub Date : 2002-11-07 DOI: 10.1109/IEMT.2002.1032738

J. Cecil, A. Kanchanapiboon, P. Kanda, A. Muthaiyan

引用次数: 12