环保,高热阻,低CTE半导体封装基板材料

T. Baba
{"title":"环保,高热阻,低CTE半导体封装基板材料","authors":"T. Baba","doi":"10.1109/IEMT.2002.1032785","DOIUrl":null,"url":null,"abstract":"Semiconductor packaging technology has been moving towards increased miniaturization, lighter weight and higher density. Flip Chip packaging is therefore becoming the mainstream packaging technology for next generation devices. The technology trend has been moving towards much finer pitch interconnections between the semiconductor chip and the package substrate, much narrower circuit width on the substrate and a much smaller diameter of the circuitry layer interconnection. Thus, concerns arise regarding mechanical and electrical deterioration and failure at the interconnections. Previously much more focus had been placed on systems utilizing Halogen-free and Pb-free raw materials in order to meet environmental requirements. In this paper, we are reporting a new substrate material for semiconductor packages (Copper-clad-laminate: ELC-4785GS, Prepreg: EI-6785GS, Build-up material: APL-4601) which Sumitomo Bakelite has begun developing.","PeriodicalId":340284,"journal":{"name":"27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Environmentally friendly, high thermal resistant, low CTE substrate material for semiconductor packaging\",\"authors\":\"T. Baba\",\"doi\":\"10.1109/IEMT.2002.1032785\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Semiconductor packaging technology has been moving towards increased miniaturization, lighter weight and higher density. Flip Chip packaging is therefore becoming the mainstream packaging technology for next generation devices. The technology trend has been moving towards much finer pitch interconnections between the semiconductor chip and the package substrate, much narrower circuit width on the substrate and a much smaller diameter of the circuitry layer interconnection. Thus, concerns arise regarding mechanical and electrical deterioration and failure at the interconnections. Previously much more focus had been placed on systems utilizing Halogen-free and Pb-free raw materials in order to meet environmental requirements. In this paper, we are reporting a new substrate material for semiconductor packages (Copper-clad-laminate: ELC-4785GS, Prepreg: EI-6785GS, Build-up material: APL-4601) which Sumitomo Bakelite has begun developing.\",\"PeriodicalId\":340284,\"journal\":{\"name\":\"27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEMT.2002.1032785\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEMT.2002.1032785","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

摘要

半导体封装技术正朝着小型化、轻量化和高密度的方向发展。因此,倒装芯片封装正成为下一代器件的主流封装技术。技术趋势是在半导体芯片和封装基板之间进行更细间距的互连,基板上更窄的电路宽度和更小直径的电路层互连。因此,出现了对机械和电气老化和互连故障的关注。以前,为了满足环境要求,更多的重点放在使用无卤和无铅原材料的系统上。在本文中,我们报告了一种用于半导体封装的新衬底材料(镀铜层压板:ELC-4785GS,预浸料:EI-6785GS,堆积材料:APL-4601),住友电木已经开始开发。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Environmentally friendly, high thermal resistant, low CTE substrate material for semiconductor packaging
Semiconductor packaging technology has been moving towards increased miniaturization, lighter weight and higher density. Flip Chip packaging is therefore becoming the mainstream packaging technology for next generation devices. The technology trend has been moving towards much finer pitch interconnections between the semiconductor chip and the package substrate, much narrower circuit width on the substrate and a much smaller diameter of the circuitry layer interconnection. Thus, concerns arise regarding mechanical and electrical deterioration and failure at the interconnections. Previously much more focus had been placed on systems utilizing Halogen-free and Pb-free raw materials in order to meet environmental requirements. In this paper, we are reporting a new substrate material for semiconductor packages (Copper-clad-laminate: ELC-4785GS, Prepreg: EI-6785GS, Build-up material: APL-4601) which Sumitomo Bakelite has begun developing.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信