Cost and manufacturing optimization of high performance communication hardware using a daughter module

Abstract

The radical rise in localized component density has forced designers to utilize extremely high density, high layer count printed circuit boards. These high layer counts make the board more difficult, and more expensive to fabricate, resulting in higher costs, reduced raw board yield and a restricted supply base of PCB shops that can build the required substrates. In many instances the need for multiple layer counts is usually limited to a small percentage of the total PCB surface area where a high I/O ASIC and its associated memory are located. To overcome these limitations, the option of removing the complex, localized, high-density routing area(s) of the circuitry and moving it to a daughter module was employed to achieve a lower cost PCB and expanded PCB supply base.