Material and process considerations for reliable overniolded flip chip PBGAs

Abstract

Recently a p a t deal of interest has arisen in the overmolding of flip chip assemblies. Reasons v q from perceived reliabiliv advantages to easier handling of thin substrates to aesthetic impressions on the final customer (making a flip chip BGA look like a wirebonded BGA). Fabricating these assemblies, in its simplest form, producing a conventional underfilled flip chip PBGG then encapsulating the entire die and surrounding substrate with a thermosetting resin by a transfer moldmg process. The appearance of such a package and its handling characteristics are practically the same as that of a wirebonded BGA. The usual unddill materials and processes are commonly employed in fabricating the underfilled assemblies, however, the imposition of a relatively constraining mold compound provides the opportunity to explore options not available to conventional flip chip PBGAs, such as very soft undedills or unfilled, fluxing underlills. These experiments attempted to define material and process l i tat ions required in assembling a package capable of JEDEC 3 (22OOC) followed by subsequent thermal cycling or autoclave testing. Assembly processes are described in detail. Reliability results are compared with those of non-molded assemblies. Success was gauged by the extent of cracking and/or delamination within the packages. Failure modes are discussed and related to underfill physical properties. Introdllction Demands for speedy and low cost packages are driving the packaging industry toward flip chip at a t e d i c rate. This once exotic packaging scheme is now being adopted industrywide as a viable, cost-effective alternative to wire bonded packages, especially for CSPs. In particular, components for portable communications and power conversion devices benefit from ilip chip technology.’ The new package must, however, adapt to existing requirements for form factor, appearance, and parts handling. That is difficult for conventional flip chip packages. They look quite Merent. The die and underfa, whose appearance may vary significantly from package to package, are o h subjected to appearance criteria unlike those of molded packages. Handling may be problematic as well, since vision and placement equipment ofien must be reconfigured to deal with the backside of the packaged die rather than the matte finish of a molded package. Damage to the die backside is commonly a concern among those handling and placing flip chip packages. For all of these reasons the switch to flip chip is more seamless if the package looks like the package that it’s replacing (often a molded array package). Molding over the die of a flip chip package removes many of the handling and appearance issues normally encountered in inboducing flip clup packaging. Mold compound gives the package a uniform, familiar appearance and M e n s the structure of the package. StSening is especially practical where very thin substrates are employed. Figure 1 shows some of the features of a so-called arraymolded flip chip CSP. One concern over the addition of a molding step is the effect on package reliability. Of special concem to the materials engineer is the interface between mold compound and undedl, since adhesion between such materials is notoriously poor. The properties of underfill and mold compound are expected to interact to produce stress states that are certainly different from those of the conventional flip chip package. In some ways the new geometry can be likened to that of a molded wirebonded BGA. In such stmctures soft, low (sub-ambient) Tg die attach materials, in comparison with the properties of common capillary underfills, commonly yield the most reliable packages.