2022 IEEE European Test Symposium (ETS)最新文献_第3页

Special Session on RF/5G Test RF/5G测试特别会议

2022 IEEE European Test Symposium (ETS) Pub Date : 2022-05-23 DOI: 10.1109/ETS54262.2022.9810461

W. Eisenstadt, M. Roos, Devin Morris, J. González-Jiménez, Christopery Mounet, M. Barragán, G. Léger, F. Cilici, E. Lauga-Larroze, S. Mir, S. Bourdel, M. Margalef-Rovira, I. Alaji, H. Ghanem, G. Ducournau, C. Gaquière

引用次数: 0

Smart Redundancy Schemes for ANNs Against Fault Attacks 针对故障攻击的人工神经网络智能冗余方案

2022 IEEE European Test Symposium (ETS) Pub Date : 2022-05-23 DOI: 10.1109/ETS54262.2022.9810380

Troya Çağıl Köylü, S. Hamdioui, M. Taouil

引用次数: 1

RRAM Crossbar-Based Fault-Tolerant Binary Neural Networks (BNNs) 基于RRAM交叉栏的容错二值神经网络

2022 IEEE European Test Symposium (ETS) Pub Date : 2022-05-23 DOI: 10.1109/ETS54262.2022.9810414

A. Gebregiorgis, Artemis Zografou, S. Hamdioui

引用次数: 1

ETS 2022 Sponsors ETS 2022赞助商

2022 IEEE European Test Symposium (ETS) Pub Date : 2022-05-23 DOI: 10.1109/ets54262.2022.9810423

引用次数: 0

Quality Assessment of RFET-based Logic Locking Protection Mechanisms using Formal Methods 基于rfet的逻辑锁定保护机制的形式化质量评估

2022 IEEE European Test Symposium (ETS) Pub Date : 2022-05-23 DOI: 10.1109/ETS54262.2022.9810459

M. Merten, S. Huhn, R. Drechsler

{"title":"Quality Assessment of RFET-based Logic Locking Protection Mechanisms using Formal Methods","authors":"M. Merten, S. Huhn, R. Drechsler","doi":"10.1109/ETS54262.2022.9810459","DOIUrl":"https://doi.org/10.1109/ETS54262.2022.9810459","url":null,"abstract":"The high distribution of the manufacturing of Integrated Circuits (ICs) over different foundries yields long and untrustworthy supply chains. Logic locking is one prominent protection technique against malicious usage and counterfeit. The emerging technology of Reconfigurable Field-Effect Transistors (RFETs) has recently been utilized to implement new polymorphic logic mechanisms to protect intellectual property. The mechanisms’ assessment is important to reinforce the newly introduced protection mechanism and, hence, avoid any weak logic structures. So far, approximate Hamming Distance-based assessment techniques have been used for determining the protection quality while considering combinatorial circuits only. This work proposes a novel method to assess the quality of the RFET-based logic locking structures for sequential circuits. In particular, formal techniques are orchestrated to analyze the circuit’s state space to determine whether any incorrect keys exist that unintentionally unlock and exhibit the circuit’s correct functional behavior. The experimental evaluation validates that the proposed scheme unveils weaknesses of the protection structure, which remain undetected when using existing techniques.","PeriodicalId":334931,"journal":{"name":"2022 IEEE European Test Symposium (ETS)","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127962782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

ETS 2021 Best Paper ETS 2021年度最佳论文

2022 IEEE European Test Symposium (ETS) Pub Date : 2022-05-23 DOI: 10.1109/ets54262.2022.9810417

引用次数: 0

A Generic Fast and Low Cost BIST Solution for CMOS Image Sensors 一种通用、快速、低成本的CMOS图像传感器BIST解决方案

2022 IEEE European Test Symposium (ETS) Pub Date : 2022-05-23 DOI: 10.1109/ETS54262.2022.9810458

J. Lefevre, P. Debaud, P. Girard, A. Virazel

{"title":"A Generic Fast and Low Cost BIST Solution for CMOS Image Sensors","authors":"J. Lefevre, P. Debaud, P. Girard, A. Virazel","doi":"10.1109/ETS54262.2022.9810458","DOIUrl":"https://doi.org/10.1109/ETS54262.2022.9810458","url":null,"abstract":"This paper demonstrates the generalization of a novel test solution embedded inside CMOS Image Sensors (CIS) to classify PASS/FAIL sensors during the test production phase. In [1], a Built-In Self-Test (BIST) solution was proposed to reduce the test time of a CIS, which can represent up to 30% of the final product cost. The major part of the test is dedicated to optical (i.e. image processsing) algorithms performed on the output images from the sensor under test with an Automatic Test Equipment (ATE). The BIST solution reuses these optical algorithms by simplifying and embedding them inside the sensor, to avoid a large amount of data storage and to limit the optical test time. First results on 4,800 output images from a package of sensors have shown a 99.95% correlation between results gathered from an ATE and those achieved with the proposed BIST, with a saving of approximately 30% in optical test time and a negligible area footprint. In this paper, to verify the effectiveness of the BIST solution on a wider set of different CIS (i.e., architecture, size and technology), we experimented the solution on a new database of 28,000 output images from a package of different sensors compared to the first package used in [1]. The BIST parameters have been configured to fit with the new type of sensors and results show a 99.64% correlation, which demonstrates the possible systematic implementation of the proposed BIST solution inside all CIS irrespective of their architecture and technology.","PeriodicalId":334931,"journal":{"name":"2022 IEEE European Test Symposium (ETS)","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116556777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Concurrent Error Detection for LSTM Accelerators LSTM加速器并发错误检测

2022 IEEE European Test Symposium (ETS) Pub Date : 2022-05-23 DOI: 10.1109/ETS54262.2022.9810369

Nooshin Nosrati, Seyedeh Maryam Ghasemi, Mahboobe Sadeghipour Roodsari, Z. Navabi

引用次数: 0

SpinalFuzz: Coverage-Guided Fuzzing for SpinalHDL Designs SpinalFuzz:覆盖引导模糊SpinalHDL设计

2022 IEEE European Test Symposium (ETS) Pub Date : 2022-05-23 DOI: 10.1109/ETS54262.2022.9810421

Katharina Ruep, Daniel Große

引用次数: 4

Machine learning based soft error rate estimation of pass transistor logic in high-speed communication 基于机器学习的高速通信通管逻辑软错误率估计

2022 IEEE European Test Symposium (ETS) Pub Date : 2022-05-23 DOI: 10.1109/ETS54262.2022.9810410

Z. Zhang, J. Lappas, A. Chinazzo, C. Weis, Z. Wu, L. Ni, N. Wehn, M. Tahoori

{"title":"Machine learning based soft error rate estimation of pass transistor logic in high-speed communication","authors":"Z. Zhang, J. Lappas, A. Chinazzo, C. Weis, Z. Wu, L. Ni, N. Wehn, M. Tahoori","doi":"10.1109/ETS54262.2022.9810410","DOIUrl":"https://doi.org/10.1109/ETS54262.2022.9810410","url":null,"abstract":"Recent advanced high-speed communication systems, such as optical systems, require highest reliability at lowest possible power consumption. Thus, Pass Transistor Logic (PTL) is gaining lots of interest in these communication systems due to its power saving potential compared to traditional CMOS logic. However, due to the non-conventional logic structure, its susceptibility to radiation-induced soft errors is different from CMOS circuitry. Due to the unique generation and propagation of Single Event Transients (SETs) in PTL, different approaches for PTL soft error rate (SER) estimation are required. In this paper we propose a machine learning (ML) approach for SET propagation in PTL logic. Multi-layer feed-forward neural network together with support vector classifier (SVC) are used to build the SET pulse width and pulse amplitude models. Bayesian optimization using Gaussian Processes is utilized to tune the hyperparameters of neural network. The experimental results on full adder (FA), which is the key component in many large cirucits such as ALU, and comparison with Monte Carlo (MC) spectre simulations confirm the accuracy and speed of the proposed method.","PeriodicalId":334931,"journal":{"name":"2022 IEEE European Test Symposium (ETS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122505151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1