W. Eisenstadt, M. Roos, Devin Morris, J. González-Jiménez, Christopery Mounet, M. Barragán, G. Léger, F. Cilici, E. Lauga-Larroze, S. Mir, S. Bourdel, M. Margalef-Rovira, I. Alaji, H. Ghanem, G. Ducournau, C. Gaquière
{"title":"Special Session on RF/5G Test","authors":"W. Eisenstadt, M. Roos, Devin Morris, J. González-Jiménez, Christopery Mounet, M. Barragán, G. Léger, F. Cilici, E. Lauga-Larroze, S. Mir, S. Bourdel, M. Margalef-Rovira, I. Alaji, H. Ghanem, G. Ducournau, C. Gaquière","doi":"10.1109/ETS54262.2022.9810461","DOIUrl":null,"url":null,"abstract":"This paper presents an innovative integrated load-pull bench at 160 GHz. The proposed system, which is designed in a 55-nm BiCMOS technology, is tailored to deal with all of the measurement functions including signal generation, shaping, and magnitude and phase measurement. This system will allow precise characterization of Devices-Under-Test (DUTs) (i.e., circuits and/or devices) when integrated together with the DUT. In addition, the proposed system could also be envisioned as a System-on-Chip (SoC) that, when reported into an RF probe, could serve as a test bench for any integrated circuit.","PeriodicalId":334931,"journal":{"name":"2022 IEEE European Test Symposium (ETS)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE European Test Symposium (ETS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ETS54262.2022.9810461","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper presents an innovative integrated load-pull bench at 160 GHz. The proposed system, which is designed in a 55-nm BiCMOS technology, is tailored to deal with all of the measurement functions including signal generation, shaping, and magnitude and phase measurement. This system will allow precise characterization of Devices-Under-Test (DUTs) (i.e., circuits and/or devices) when integrated together with the DUT. In addition, the proposed system could also be envisioned as a System-on-Chip (SoC) that, when reported into an RF probe, could serve as a test bench for any integrated circuit.