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On the Impact of Hardware Timing Errors on Stochastic Computing based Neural Networks 硬件时序误差对基于随机计算的神经网络的影响
2022 IEEE European Test Symposium (ETS) Pub Date : 2022-05-23 DOI: 10.1109/ETS54262.2022.9810429
Florian Neugebauer, S. Holst, I. Polian
{"title":"On the Impact of Hardware Timing Errors on Stochastic Computing based Neural Networks","authors":"Florian Neugebauer, S. Holst, I. Polian","doi":"10.1109/ETS54262.2022.9810429","DOIUrl":"https://doi.org/10.1109/ETS54262.2022.9810429","url":null,"abstract":"Stochastic computing (SC) with its stream-based, probabilistic number representation promises large area and power benefits as well as increased error tolerance compared to conventional binary computing. While SC is less precise, it is considered a promising option for implementing neural network inferencing in ultra-low-power edge devices. SC-based Neural Networks (SCNNs) typically combine stochastic and binary components for interfacing and to alleviate certain SC limitations. Moreover, ultra-low-power VLSI for edge computing is often less reliable due to noisy environments or deliberate power-reliability trade-offs. In this work, we present the first detailed investigation of the behavior of an SCNN and its individual components on hardware prone to timing errors. Our results show that robustness of SC is highly dependent on specific design choices and that biases in the error distributions may even cause SCNNs to perform worse under certain circumstances than comparable binary implementations. It shows that robustness should be treated as a design goal in SC rather than taken for granted.","PeriodicalId":334931,"journal":{"name":"2022 IEEE European Test Symposium (ETS)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132529972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Power Aware Test 电源感知测试
2022 IEEE European Test Symposium (ETS) Pub Date : 2022-05-23 DOI: 10.1109/ETS54262.2022.9810367
Likith Kumar Manchukonda, Karthikeyan Natarajan, Manish Arora
{"title":"Power Aware Test","authors":"Likith Kumar Manchukonda, Karthikeyan Natarajan, Manish Arora","doi":"10.1109/ETS54262.2022.9810367","DOIUrl":"https://doi.org/10.1109/ETS54262.2022.9810367","url":null,"abstract":"Power handling during test is an important requirement that needs to be considered during chip design, silicon bring-up, and in-system testing. In this tutorial, we will start by reviewing the importance of power and listing the different problems faced with poor power intent. We will then give an overview of different power aspects related to test, from RTL implementation to in-system validation, and how each step can impact the overall performance. Next, we will introduce different design-for-test (DFT) techniques that help improve power planning to produce optimized quality of results (QoR). Finally, we will present data sets on how each of the listed techniques implemented on real designs produces desired results.","PeriodicalId":334931,"journal":{"name":"2022 IEEE European Test Symposium (ETS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133681202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Effective techniques for automatically improving the transition delay fault coverage of Self-Test Libraries 自动提高自测试库转换延迟故障覆盖率的有效技术
2022 IEEE European Test Symposium (ETS) Pub Date : 2022-05-23 DOI: 10.1109/ETS54262.2022.9810392
R. Cantoro, Francesco Garau, P. Girard, Nima Kolahimahmoudi, Sandro Sartoni, M. Reorda, A. Virazel
{"title":"Effective techniques for automatically improving the transition delay fault coverage of Self-Test Libraries","authors":"R. Cantoro, Francesco Garau, P. Girard, Nima Kolahimahmoudi, Sandro Sartoni, M. Reorda, A. Virazel","doi":"10.1109/ETS54262.2022.9810392","DOIUrl":"https://doi.org/10.1109/ETS54262.2022.9810392","url":null,"abstract":"In-field test of integrated circuits using Self-Test Libraries (STLs) is a widely used technique specifically suited to guarantee the processor’s correct behavior during the operative lifetime, as mandated by functional safety standards such as ISO26262. Developing STLs for stuck-at faults requires significant manual efforts from test engineers, and targeting delay faults is even more challenging. In order to support this process, in this paper we propose a method to automate the creation of STLs targeting delay faults starting from existing STLs targeting stuck-at faults. The method is based first on identifying excited but not-observed transition delay faults and then adding suitable instructions able to detect them. Experimental results on a RISC-V processor show that the method can systematically detect a significant percentage of the target faults with reasonable computational effort and test code size increase.","PeriodicalId":334931,"journal":{"name":"2022 IEEE European Test Symposium (ETS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115580031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
ETS 2022 Foreword
2022 IEEE European Test Symposium (ETS) Pub Date : 2022-05-23 DOI: 10.1109/ets54262.2022.9810450
{"title":"ETS 2022 Foreword","authors":"","doi":"10.1109/ets54262.2022.9810450","DOIUrl":"https://doi.org/10.1109/ets54262.2022.9810450","url":null,"abstract":"On behalf of the Program, Organizing, and Steering Committees, we are pleased to extend a warm welcome to all participants in the European Test Symposium 2022 (ETS'22). ETS has consolidated as one of the leading international forums that calls together the testing community to promote the exchange and discussion of scientific results, emerging ideas, applications, hot topics and new trends in the area of electronic-based circuits and systems reliability, safety, security and validation.","PeriodicalId":334931,"journal":{"name":"2022 IEEE European Test Symposium (ETS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114280740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
AMS Test Vector Generation using AMS Verification and IEEE P1687.2 使用AMS验证和IEEE P1687.2生成AMS测试向量
2022 IEEE European Test Symposium (ETS) Pub Date : 2022-05-23 DOI: 10.1109/ETS54262.2022.9810471
V. Zivkovic, M. Palazzi, Ming Chuen Alvan Lam, Mogens Isager
{"title":"AMS Test Vector Generation using AMS Verification and IEEE P1687.2","authors":"V. Zivkovic, M. Palazzi, Ming Chuen Alvan Lam, Mogens Isager","doi":"10.1109/ETS54262.2022.9810471","DOIUrl":"https://doi.org/10.1109/ETS54262.2022.9810471","url":null,"abstract":"This paper presents a powerful combination of Analog Mixed-Signal (AMS) verification in combination with emerging IEEE P1687.2 standard, capable of enabling automation of the large part of test pattern generation flow from the specification to Automatic Test Equipment (ATE). The inherent property of AMS verification to incorporate UVM based environment and a configuration with design modules described at arbitrary abstraction levels allows efficient pre-silicon test setup simulation. UVM also facilitates automated generation of STIL, used as the main vehicle to trigger various ATE instruments. The approach is piloted on a power amplifier product that contains BigA and not-so-small D portion. To the best of our knowledge, this is the first proposed self-containing flow that achieves test development reduction and provides guidance for test quality improvement while relying entirely on emerging and existing IEEE standards.","PeriodicalId":334931,"journal":{"name":"2022 IEEE European Test Symposium (ETS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114213819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
X-Masking for In-System Deterministic Test 系统内确定性测试的x屏蔽
2022 IEEE European Test Symposium (ETS) Pub Date : 2022-05-23 DOI: 10.1109/ETS54262.2022.9810407
Grzegorz Mrugalski, J. Rajski, J. Tyszer, Bartosz Wlodarczak
{"title":"X-Masking for In-System Deterministic Test","authors":"Grzegorz Mrugalski, J. Rajski, J. Tyszer, Bartosz Wlodarczak","doi":"10.1109/ETS54262.2022.9810407","DOIUrl":"https://doi.org/10.1109/ETS54262.2022.9810407","url":null,"abstract":"In-system deterministic tests are used in safety-sensitive designs to assure high test coverage, short test time, and low data volume, typically through an input-streaming-only approach that allows a quick test delivery. The output side of the same scheme is, however, inherently vulnerable to unknown (X) states whose sources vary from uninitialized memory elements to the last-minute timing violations. Typically, X values degrade test results and thus test response compaction requires some form of protection. This paper presents two X-masking schemes that complement the primary (or level-A) blocking of unknown values by filtering out those X states that escape the first stage of masking and shall not reach a test response compactor or test result sticky-bits deployed by the on-chip compare framework. Experimental results obtained for eleven industrial designs show feasibility and efficiency of the proposed schemes altogether with actual impact of X-masking on various test-related statistics.","PeriodicalId":334931,"journal":{"name":"2022 IEEE European Test Symposium (ETS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114237817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
ETS 2022 Distinguished Service Award ETS 2022年杰出服务奖
2022 IEEE European Test Symposium (ETS) Pub Date : 2022-05-23 DOI: 10.1109/ets54262.2022.9810448
{"title":"ETS 2022 Distinguished Service Award","authors":"","doi":"10.1109/ets54262.2022.9810448","DOIUrl":"https://doi.org/10.1109/ets54262.2022.9810448","url":null,"abstract":"","PeriodicalId":334931,"journal":{"name":"2022 IEEE European Test Symposium (ETS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127141003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Lightweight, Plug-and-Play and Autonomous JTAG Authentication IP for Secure Device Testing 用于安全设备测试的轻量级，即插即用和自主JTAG认证IP
2022 IEEE European Test Symposium (ETS) Pub Date : 2022-05-23 DOI: 10.1109/ETS54262.2022.9810364
S. Lapeyre, Nicolas Valette, Marc Merandat, M. Flottes, A. Virazel, B. Rouzeyre
{"title":"A Lightweight, Plug-and-Play and Autonomous JTAG Authentication IP for Secure Device Testing","authors":"S. Lapeyre, Nicolas Valette, Marc Merandat, M. Flottes, A. Virazel, B. Rouzeyre","doi":"10.1109/ETS54262.2022.9810364","DOIUrl":"https://doi.org/10.1109/ETS54262.2022.9810364","url":null,"abstract":"As any other circuits, secure devices need to be tested to ensure their reliability. Nevertheless, test infrastructures, such as JTAG or scan chains, can maliciously be used to steal secret data stored or processed in secure devices. In this paper, we explore a lightweight solution to protect JTAG access based on a challenge-response authentication protocol. A JTAG-authentication dedicated IP is presented. Design alternatives for quick IP plug-and-play, security, area and test time optimization are presented and evaluated.","PeriodicalId":334931,"journal":{"name":"2022 IEEE European Test Symposium (ETS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130931198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Data-driven Approach for Fault Detection in the Alternator Unit of Automotive Systems 汽车系统交流机组故障检测的数据驱动方法
2022 IEEE European Test Symposium (ETS) Pub Date : 2022-05-23 DOI: 10.1109/ETS54262.2022.9810432
Arunkumar Vijayan, M. Tahoori, Ewald Kintzli, T. Lohmann, Juergen Hans Handl
{"title":"A Data-driven Approach for Fault Detection in the Alternator Unit of Automotive Systems","authors":"Arunkumar Vijayan, M. Tahoori, Ewald Kintzli, T. Lohmann, Juergen Hans Handl","doi":"10.1109/ETS54262.2022.9810432","DOIUrl":"https://doi.org/10.1109/ETS54262.2022.9810432","url":null,"abstract":"Functional safety is considered as a prominent dependability attribute in today’s automotive world. It is extremely important to ensure safe operation of different automotive parts. An alternator unit is an electric generator used in modern automobiles to charge the battery and to power the electrical system when its engine is running. Therefore, its correct operation is crucial for the overall automobile safety. In this work, we predict the health of an alternator on-the-fly using machine learning approaches for efficient yet accurate failure detection. We make use of inexpensive time domain features of alternator voltage waveform to achieve 97% prediction accuracy with no false positives. The correctness and usability of the proposed approach has been validated using realistic testing environment.","PeriodicalId":334931,"journal":{"name":"2022 IEEE European Test Symposium (ETS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133356333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
AI-Assisted Yield Learning 人工智能辅助产量学习
2022 IEEE European Test Symposium (ETS) Pub Date : 2022-05-23 DOI: 10.1109/ets54262.2022.9810408
{"title":"AI-Assisted Yield Learning","authors":"","doi":"10.1109/ets54262.2022.9810408","DOIUrl":"https://doi.org/10.1109/ets54262.2022.9810408","url":null,"abstract":"","PeriodicalId":334931,"journal":{"name":"2022 IEEE European Test Symposium (ETS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132316492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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