Power Aware Test

Abstract

Power handling during test is an important requirement that needs to be considered during chip design, silicon bring-up, and in-system testing. In this tutorial, we will start by reviewing the importance of power and listing the different problems faced with poor power intent. We will then give an overview of different power aspects related to test, from RTL implementation to in-system validation, and how each step can impact the overall performance. Next, we will introduce different design-for-test (DFT) techniques that help improve power planning to produce optimized quality of results (QoR). Finally, we will present data sets on how each of the listed techniques implemented on real designs produces desired results.