Quality Assessment of RFET-based Logic Locking Protection Mechanisms using Formal Methods

M. Merten, S. Huhn, R. Drechsler
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引用次数: 3

Abstract

The high distribution of the manufacturing of Integrated Circuits (ICs) over different foundries yields long and untrustworthy supply chains. Logic locking is one prominent protection technique against malicious usage and counterfeit. The emerging technology of Reconfigurable Field-Effect Transistors (RFETs) has recently been utilized to implement new polymorphic logic mechanisms to protect intellectual property. The mechanisms’ assessment is important to reinforce the newly introduced protection mechanism and, hence, avoid any weak logic structures. So far, approximate Hamming Distance-based assessment techniques have been used for determining the protection quality while considering combinatorial circuits only. This work proposes a novel method to assess the quality of the RFET-based logic locking structures for sequential circuits. In particular, formal techniques are orchestrated to analyze the circuit’s state space to determine whether any incorrect keys exist that unintentionally unlock and exhibit the circuit’s correct functional behavior. The experimental evaluation validates that the proposed scheme unveils weaknesses of the protection structure, which remain undetected when using existing techniques.
基于rfet的逻辑锁定保护机制的形式化质量评估
集成电路(ic)的制造高度分布在不同的代工厂产生了长而不可靠的供应链。逻辑锁定是一种重要的防止恶意使用和假冒的保护技术。可重构场效应晶体管(Reconfigurable Field-Effect transistor, rfet)这一新兴技术最近被用于实现新的多态逻辑机制以保护知识产权。机制的评估对于加强新引入的保护机制非常重要,从而避免任何薄弱的逻辑结构。到目前为止,基于近似汉明距离的评估技术仅用于确定组合电路的保护质量。这项工作提出了一种新的方法来评估时序电路中基于rfet的逻辑锁定结构的质量。具体地说,正式的技术被用于分析电路的状态空间,以确定是否存在不正确的键,这些键无意中解锁并显示电路的正确功能行为。实验评估验证了该方案揭示了现有技术无法检测到的保护结构的弱点。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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