LSTM加速器并发错误检测

Nooshin Nosrati, Seyedeh Maryam Ghasemi, Mahboobe Sadeghipour Roodsari, Z. Navabi
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引用次数: 0

摘要

在与时间序列相关的应用中,长短期记忆(LSTM)加速器的广泛使用需要使用一种保护机制来防止磨损和环境影响引起的故障。本文提出了一种结合低开销复制码和剩余码的并发错误检测方案,用于LSTM加速器的乘级和加级故障检测。对于乘法阶段,CED由每个LSTM乘法器的乘法器组成,该乘法器具有数据的临时选择。对于添加阶段,CED加法器在LSTM加法器之间共享,因此执行空间选择。实验结果表明,与传统的不加区分地复制所有硬件结构的复制技术相比,该方法具有较好的检测概率和较低的面积和功耗开销。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Concurrent Error Detection for LSTM Accelerators
The widespread usage of Long Short-Term Memory (LSTM) accelerators in time-series related applications necessitates using a protection mechanism against faults caused by wear-out and environmental effects. This paper proposes a Concurrent Error Detection (CED) scheme combining low overhead duplication and residue codes to detect faults in multiply and add stages of LSTM accelerators. For the multiply stage, the CED consists of a multiplier for every LSTM multiplier with a temporal selection of data. For the add stage, the CED adders are shared among the LSTM adders, thus spatial selection is performed. The experimental results show that the proposed method yields good detection probability with a lower area and power overhead in comparison with the traditional duplication techniques that indiscriminately duplicate all hardware structures all the time.
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