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Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646)最新文献

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On using deterministic test sets in BIST 确定性测试集在物理科学技术中的应用
Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646) Pub Date : 2000-07-03 DOI: 10.1109/OLT.2000.856624
O. Novák, J. Nosek
{"title":"On using deterministic test sets in BIST","authors":"O. Novák, J. Nosek","doi":"10.1109/OLT.2000.856624","DOIUrl":"https://doi.org/10.1109/OLT.2000.856624","url":null,"abstract":"The test pattern generators (TPG) in BIST usually generate pseudorandom patterns and after the pseudorandom testing phase the random resistant faults are detected bp additional deterministic test vectors which can be compressed by the means of the same TPG. Another possibility is to optimise the TPG structure so that the generated test set contains all the necessary deterministic test vectors which detect hard-to-test faults. The vectors are obtained by the means of TPG output modifications. This approach is not acceptable for large circuits because of additional delay caused by the output combinational logic. We have proposed a TPG that has a very simple structure and in which the patterns covering the random resistant faults are generated by the TPG without any output modifying logic. The TPG sequence is controlled by XORing the pre-computed modifying bits with one of the TPG internal flip-flop input. Finding the modifying bits is done by an algorithm which optimises the fault coverage gain which is obtained by each of the generated test vectors. Several experiments were done with the ISCAS 85 and 89 benchmark circuits. The storage capacity needed for storing the modifying bits of the exercised circuits is low while the test application time is short.","PeriodicalId":334770,"journal":{"name":"Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646)","volume":"362 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133197964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Self-checking FSM design with observing only FSM outputs 只观察FSM输出的自检FSM设计
Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646) Pub Date : 2000-07-03 DOI: 10.1109/OLT.2000.856629
A. Matrosova, S. Ostanin
{"title":"Self-checking FSM design with observing only FSM outputs","authors":"A. Matrosova, S. Ostanin","doi":"10.1109/OLT.2000.856629","DOIUrl":"https://doi.org/10.1109/OLT.2000.856629","url":null,"abstract":"We deal with the problem of a self-checking FSM design with observing only FSM outputs. We suggest a special PLA description of the FSM behavior that is well suited in practice. It is established that a factorized multilevel synthesis method applied to this PLA description and followed by the gate implementation provides observing only FSM outputs. We assume that a set of faults considered does not demand introducing additional FSA input lines. We also propose a mathematical tool that makes possible for any synthesis method applied to this special PLA description to clarify the possibility of observing only FSM outputs.","PeriodicalId":334770,"journal":{"name":"Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122437001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
On realization of fault-tolerant fuzzy controllers 容错模糊控制器的实现
Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646) Pub Date : 2000-07-03 DOI: 10.1109/OLT.2000.856635
N. Kamiura, M. Tomita, T. Isokawa, N. Matsui
{"title":"On realization of fault-tolerant fuzzy controllers","authors":"N. Kamiura, M. Tomita, T. Isokawa, N. Matsui","doi":"10.1109/OLT.2000.856635","DOIUrl":"https://doi.org/10.1109/OLT.2000.856635","url":null,"abstract":"In this paper, we propose concurrent compensation for fuzzy controllers. The concurrent fault location is executed by observing each sum of two degrees of adjacent membership functions. Instead of the faulty degree in the antecedent part, we employ either 0 or degree of next membership function to the faulty part at the easily calculated abscissa. To compensate the faults in the consequent part, we shift several fuzzy variables, and infer with the membership functions representing the variables after shifts. The amount of shifting the variables is determined systematically. Experimental results show that our method is valid for any non-redundant single stuck-at fault both in each of the antecedent parts and in the consequent part.","PeriodicalId":334770,"journal":{"name":"Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126234569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Relation between fault tolerance and reconfiguration in cellular systems 元胞系统容错与重构的关系
Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646) Pub Date : 2000-07-03 DOI: 10.1109/OLT.2000.856607
L. Sekanina, V. Drábek
{"title":"Relation between fault tolerance and reconfiguration in cellular systems","authors":"L. Sekanina, V. Drábek","doi":"10.1109/OLT.2000.856607","DOIUrl":"https://doi.org/10.1109/OLT.2000.856607","url":null,"abstract":"Recently, hardware researchers have promptly begun to investigate alternative computational principles to the conventional ones. The main signs of these principles are inspiration in biology and their direct hardware implementation. Evolvable hardware, cellular computing or embryonic electronics are the most important examples. This paper describes different approaches to configuration, reconfiguration and fault tolerance implementation of two-dimensional cellular system. Simplicity of the cell, vast parallelism, and the connection locality are considered as the design restrictions.","PeriodicalId":334770,"journal":{"name":"Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130927407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Power reduction in test-per-scan BIST 每扫描一次测试的BIST功耗降低
Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646) Pub Date : 2000-07-03 DOI: 10.1109/OLT.2000.856625
Xiaodong Zhang, K. Roy
{"title":"Power reduction in test-per-scan BIST","authors":"Xiaodong Zhang, K. Roy","doi":"10.1109/OLT.2000.856625","DOIUrl":"https://doi.org/10.1109/OLT.2000.856625","url":null,"abstract":"The input signal activities during test can be much higher than during test. Hence, it is important to reduce power consumption to avoid any failures during test. In this paper, we propose techniques to reduce power dissipations in both the combinational block and the scan chain for test-per-scan BIST. Some extra circuitry is introduced between the combinational logic and the scan chain to make the combinational block idle during the scan-in and scan-out operation, and the scan chain is re-ordered so that the number of signal transitions in it is minimized. Compared to the standard weighted random pattern (WRP) testing (without re-ordering), the number of signal transitions in the scan chain can be reduced by 43.8%. With some extra circuitry, the power dissipation in the combinational block can be reduced to less than 0.86%, compared to the standard test-per-scan BIST.","PeriodicalId":334770,"journal":{"name":"Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126083014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 49
Transient bitflip injection in microprocessor embedded applications 微处理器嵌入式应用中的瞬态位翻转注入
Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646) Pub Date : 2000-07-03 DOI: 10.1109/OLT.2000.856616
R. Velazco, S. Rezgui
{"title":"Transient bitflip injection in microprocessor embedded applications","authors":"R. Velazco, S. Rezgui","doi":"10.1109/OLT.2000.856616","DOIUrl":"https://doi.org/10.1109/OLT.2000.856616","url":null,"abstract":"This paper investigates a new methodology for transient bitflip injection, randomly in time and location, in microprocessor-based digital architectures. Experimental results performed on two different architectures illustrate the potentials of this new strategy.","PeriodicalId":334770,"journal":{"name":"Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133521983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
1-V fast I/sub DDQ/ current sensor for on-line mixed-signal/analog test 用于在线混合信号/模拟测试的1-V快速I/sub DDQ/电流传感器
Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646) Pub Date : 2000-07-03 DOI: 10.1109/OLT.2000.856618
M. Margala, S. Dragic, Ahmed El-Abasiry, S. Ekpe, V. Stopjaková
{"title":"1-V fast I/sub DDQ/ current sensor for on-line mixed-signal/analog test","authors":"M. Margala, S. Dragic, Ahmed El-Abasiry, S. Ekpe, V. Stopjaková","doi":"10.1109/OLT.2000.856618","DOIUrl":"https://doi.org/10.1109/OLT.2000.856618","url":null,"abstract":"This paper proposes a novel, ultra low-voltage design of a built-in current sensor for testing mixed-signal circuits. Designed in 0.18 /spl mu/ CMOS technology, the monitor is based on the principle of a current mirror that is supported by the converting and output stages. The design is easily applicable in testing mixed-signal circuits. The sensor is designed for the power supply of 1.0 V that offers acceptance in low-voltage test applications. Presented results demonstrate excellent performances of the on-chip monitor.","PeriodicalId":334770,"journal":{"name":"Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133783061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A new method for concurrent checking by use of a 1-out-of-4 code 一种使用1 / 4代码进行并发检查的新方法
Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646) Pub Date : 2000-07-03 DOI: 10.1109/OLT.2000.856627
M. Gössel, A. Dmitriev, V. Saposhnikov, V. Saposhnikov
{"title":"A new method for concurrent checking by use of a 1-out-of-4 code","authors":"M. Gössel, A. Dmitriev, V. Saposhnikov, V. Saposhnikov","doi":"10.1109/OLT.2000.856627","DOIUrl":"https://doi.org/10.1109/OLT.2000.856627","url":null,"abstract":"In this paper a new method for concurrent checking is proposed. For an arbitrarily given combinational circuit f an additional complementary circuit g is determined such that for every input the componentwise modulo 2 sum of the corresponding outputs of f and g is an element of a considered cone as long as no error occurs. The new method of concurrent checking is developed for the concrete case of 1-out-of-4 codes.","PeriodicalId":334770,"journal":{"name":"Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121139053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A very flexible DSP-based controller for on-line test and control of industrial processes 一个非常灵活的基于dsp的控制器，用于工业过程的在线测试和控制
Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646) Pub Date : 2000-07-03 DOI: 10.1109/OLT.2000.856634
M. Nillesen, A. D. Pizzo, M. Pasquariello, R. Rizzo
{"title":"A very flexible DSP-based controller for on-line test and control of industrial processes","authors":"M. Nillesen, A. D. Pizzo, M. Pasquariello, R. Rizzo","doi":"10.1109/OLT.2000.856634","DOIUrl":"https://doi.org/10.1109/OLT.2000.856634","url":null,"abstract":"This paper presents a very flexible digital signal processor-based controller. The flexible structure of this controller permits not only an implementation of many kind of different control algorithms, but will permit also on-line tests of industrial processes. The flexibility is given by a modular structure, i.e., the controller can be adapted to the requirements of the control or test algorithm. First a description will be given of the system and finally, a possible implementation of an automotive test system will be presented. The flexible controller will especially be interesting for research and development projects, since its modularity and flexibility will permit a lot of freedom in implementing new control and test algorithms.","PeriodicalId":334770,"journal":{"name":"Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122964456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A study of the effects of transient fault injection into the VHDL model of a fault-tolerant microcomputer system 暂态故障注入对容错微机系统VHDL模型的影响研究
Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646) Pub Date : 2000-07-03 DOI: 10.1109/OLT.2000.856615
D. Gil, J. Gracia, J. Baraza, P. Gil
{"title":"A study of the effects of transient fault injection into the VHDL model of a fault-tolerant microcomputer system","authors":"D. Gil, J. Gracia, J. Baraza, P. Gil","doi":"10.1109/OLT.2000.856615","DOIUrl":"https://doi.org/10.1109/OLT.2000.856615","url":null,"abstract":"This work presents a campaign of fault injection to validate the dependability of a fault tolerant microcomputer system. The system is duplex with cold stand-by sparing, parity detection and a watchdog timer. The faults have been injected on a chip-level VHDL model, using an injection tool designed for this purpose. We have carried out a set of injection experiments (with 3000 injections each), injecting transient faults of types stuck-at, bit-flip, indetermination and delay on both the signals and variables of the system, running two different workloads. We have analysed the pathology of the propagated errors, measured their latency, and calculated both detection and recovery coverage. For instance, system detection coverages (including non-effective errors) up to 98%, and system recovery coverage up to 94% have been obtained for short transient faults.","PeriodicalId":334770,"journal":{"name":"Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130317470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
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