每扫描一次测试的BIST功耗降低

Xiaodong Zhang, K. Roy
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引用次数: 49

摘要

测试期间的输入信号活动可以比测试期间高得多。因此,降低功耗以避免测试过程中的任何故障是很重要的。在本文中,我们提出了在组合块和扫描链中降低每扫描一次测试的BIST功耗的技术。在组合逻辑和扫描链之间引入了一些额外的电路,使组合块在扫描输入和扫描输出过程中空闲,并对扫描链进行了重新排序,使其中的信号转换次数最小化。与标准加权随机模式(WRP)测试(不重新排序)相比,扫描链中的信号转换次数减少了43.8%。通过一些额外的电路,与标准的每扫描一次测试的BIST相比,组合块中的功耗可以降低到0.86%以下。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Power reduction in test-per-scan BIST
The input signal activities during test can be much higher than during test. Hence, it is important to reduce power consumption to avoid any failures during test. In this paper, we propose techniques to reduce power dissipations in both the combinational block and the scan chain for test-per-scan BIST. Some extra circuitry is introduced between the combinational logic and the scan chain to make the combinational block idle during the scan-in and scan-out operation, and the scan chain is re-ordered so that the number of signal transitions in it is minimized. Compared to the standard weighted random pattern (WRP) testing (without re-ordering), the number of signal transitions in the scan chain can be reduced by 43.8%. With some extra circuitry, the power dissipation in the combinational block can be reduced to less than 0.86%, compared to the standard test-per-scan BIST.
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