On using deterministic test sets in BIST

O. Novák, J. Nosek
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引用次数: 5

Abstract

The test pattern generators (TPG) in BIST usually generate pseudorandom patterns and after the pseudorandom testing phase the random resistant faults are detected bp additional deterministic test vectors which can be compressed by the means of the same TPG. Another possibility is to optimise the TPG structure so that the generated test set contains all the necessary deterministic test vectors which detect hard-to-test faults. The vectors are obtained by the means of TPG output modifications. This approach is not acceptable for large circuits because of additional delay caused by the output combinational logic. We have proposed a TPG that has a very simple structure and in which the patterns covering the random resistant faults are generated by the TPG without any output modifying logic. The TPG sequence is controlled by XORing the pre-computed modifying bits with one of the TPG internal flip-flop input. Finding the modifying bits is done by an algorithm which optimises the fault coverage gain which is obtained by each of the generated test vectors. Several experiments were done with the ISCAS 85 and 89 benchmark circuits. The storage capacity needed for storing the modifying bits of the exercised circuits is low while the test application time is short.
确定性测试集在物理科学技术中的应用
测试模式发生器(TPG)通常生成伪随机模式,在伪随机测试阶段后,通过附加的确定性测试向量来检测随机抗故障,这些确定性测试向量可以通过相同的TPG进行压缩。另一种可能性是优化TPG结构,以便生成的测试集包含所有必要的确定性测试向量,以检测难以测试的故障。矢量是通过TPG输出修正得到的。这种方法不适用于大型电路,因为输出组合逻辑会造成额外的延迟。我们提出了一种结构非常简单的TPG,其中覆盖随机电阻故障的模式由TPG生成,不需要任何输出修改逻辑。TPG序列通过将预先计算的修改位与TPG内部触发器输入中的一个进行XORing来控制。通过优化由每个生成的测试向量获得的故障覆盖增益的算法来查找修改位。在iscas85和89基准电路上进行了多次实验。在测试应用时间短的情况下,用于存储所练习电路的修改位所需的存储容量低。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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