V. Pouget, P. Fouillat, D. Lewis, H. Lapuyade, L. Sarger, F. M. Roche, S. Duzellier, R. Ecoffet
{"title":"An overview of the applications of a pulsed laser system for SEU testing","authors":"V. Pouget, P. Fouillat, D. Lewis, H. Lapuyade, L. Sarger, F. M. Roche, S. Duzellier, R. Ecoffet","doi":"10.1109/OLT.2000.856612","DOIUrl":"https://doi.org/10.1109/OLT.2000.856612","url":null,"abstract":"This paper presents several recent results concerning single-event upset testing with a pulsed laser. It includes sensitivity mapping of an test SRAM cell, slave-induced upset in a flip-flop, MBU mapping of a 16 Mbit DRAM, and online testing of a sequencer-counter.","PeriodicalId":334770,"journal":{"name":"Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130475992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A compact built-in current sensor for I/sub DDQ/ testing","authors":"Y. Tsiatouhas, T. Haniotakis, D. Nikolos","doi":"10.1109/OLT.2000.856619","DOIUrl":"https://doi.org/10.1109/OLT.2000.856619","url":null,"abstract":"In this paper a simple to implement, compact, build-in current sensor for I/sub DDQ/ testing of CMOS VLSI circuits based on current mirroring techniques is proposed. This sensor can attain small detection times and can be used for both on-line and off-line I/sub DDQ/ testing.","PeriodicalId":334770,"journal":{"name":"Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121018635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Self-testing of FPGA delay faults in the system environment","authors":"A. Krasniewski","doi":"10.1109/OLT.2000.856610","DOIUrl":"https://doi.org/10.1109/OLT.2000.856610","url":null,"abstract":"We propose a procedure for self-testing of an FPGA programmed to implement a user-defined function. The procedure is intended to improve the detectability of FPGA delay faults. This improvement is obtained by modifying the functions of LUTs in the section under test, so that each LUT implements a XOR function. We show that, despite many potential problems, the proposed modification can significantly enhance the susceptibility of FPGA delay faults to random testing.","PeriodicalId":334770,"journal":{"name":"Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115368332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Girard, C. Landrault, S. Pravossoudovitch, A. Virazel
{"title":"Comparison between random and pseudo-random generation for BIST of delay, stuck-at and bridging faults","authors":"P. Girard, C. Landrault, S. Pravossoudovitch, A. Virazel","doi":"10.1109/OLT.2000.856623","DOIUrl":"https://doi.org/10.1109/OLT.2000.856623","url":null,"abstract":"The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. As delay testing using external testers requires expensive ATE, built-in self test (BIST) is an alternative technique that can significantly reduce the test cost. The generation of test patterns in this case is usually pseudo-random (produced from an LFSR), and it has been proven that Single Input Change (SIC) test sequences are more effective than classical Multiple Input Change (MIC) test sequences when a high robust delay fault coverage is targeted. In this paper, we first question the use of a pseudo-random generation to produce effective delay test pairs. We demonstrate that using truly random test pairs (produced from a software generation) to test path delay faults in a given circuit produces higher delay fault coverage than that obtained with pseudo-random test pairs obtained from a classical primitive LFSR. Next, we show that the same conclusion can be drawn when stuck-at or bridging fault coverage is targeted rather delay fault coverage. A modified hardware TPG structure allowing the generation of truly random test patterns is introduced at the end of the paper.","PeriodicalId":334770,"journal":{"name":"Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130667601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Abramovici, C. Stroud, Brandon Skaggs, J. Emmert
{"title":"Improving on-line BIST-based diagnosis for roving STARs","authors":"M. Abramovici, C. Stroud, Brandon Skaggs, J. Emmert","doi":"10.1109/OLT.2000.856608","DOIUrl":"https://doi.org/10.1109/OLT.2000.856608","url":null,"abstract":"We present improvements to our on-line BIST-based diagnosis technique originally used in the roving STARs approach. The enhanced technique starts with a new method of analyzing the BIST results, and employs the original divide-and-conquer method as a second phase only when the first phase fails or it does not achieve maximum diagnostic resolution. The combined technique significantly reduces the diagnosis time, improves the resolution in several cases, and also requires less fault-free resources.","PeriodicalId":334770,"journal":{"name":"Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130678736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Vallino, A. Dandache, J. Delahaye, F. Monteiro, B. Lepley
{"title":"A stamping technique to increase the error correction capacity of the (127,k,d) RS code","authors":"T. Vallino, A. Dandache, J. Delahaye, F. Monteiro, B. Lepley","doi":"10.1109/OLT.2000.856632","DOIUrl":"https://doi.org/10.1109/OLT.2000.856632","url":null,"abstract":"This paper presents a study of a stamping technique which allows an increase in the error-correction capacity of the (127,k,d) Reed-Solomon code. The decoding algorithm works on errors or on erasures or both. Furthermore, the error detection is still possible when the RS code is overflowed. The error-connection capacity has been evaluated for different Hamming distances \"d\" for the (127,k,d) RS stamped code. The evaluation was done through simulations using binary files representing real data from diversified environments. The simulation results are in good agreement with analytical results.","PeriodicalId":334770,"journal":{"name":"Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133958945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Micro-checkpointing: checkpointing for multithreaded applications","authors":"K. Whisnant, Z. Kalbarczyk, R. Iyer","doi":"10.1109/OLT.2000.856604","DOIUrl":"https://doi.org/10.1109/OLT.2000.856604","url":null,"abstract":"In this paper we introduce an efficient technique for checkpointing multithreaded applications. Our approach makes use of processes constructed around the ARMOR (Adaptive Reconfigurable Mobile Objects of Reliability) paradigm implemented in our Chameleon testbed. ARMOR processes are composed of disjoint elements (objects) with controlled manipulation of element state. These characteristics of ARMORS allow the process state to be collected during runtime in an efficient manner and saved to disk when necessary. We call this approach micro-checkpointing. We demonstrate micro-checkpointing in the Chameleon testbed, an environment for developing reliable distributed applications. Our results show that the overhead ranges from between 39% to 141% with an aggressive checkpointing policy, depending upon the degree to which the process conforms to our ARMOR paradigm.","PeriodicalId":334770,"journal":{"name":"Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646)","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134101255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"High level synthesis methodology for on-line testability optimization","authors":"M. A. Naal, E. Simeu","doi":"10.1109/OLT.2000.856637","DOIUrl":"https://doi.org/10.1109/OLT.2000.856637","url":null,"abstract":"Introducing testability considerations as soon as possible in the design process results in more testable design with reduced area overhead. A very important improvements can be carried out before the scheduling step. An optimization which takes effect at behavioral specifications and leads to production of an improved scheduling is proposed by this study. This optimization is good for improving not only on-line testability but also for some other objectives in the obtained synthesis.","PeriodicalId":334770,"journal":{"name":"Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132594970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B. Parrotta, M. Rebaudengo, M. Reorda, M. Violante
{"title":"New techniques for accelerating fault injection in VHDL descriptions","authors":"B. Parrotta, M. Rebaudengo, M. Reorda, M. Violante","doi":"10.1109/OLT.2000.856613","DOIUrl":"https://doi.org/10.1109/OLT.2000.856613","url":null,"abstract":"Simulation-based fault injection in VHDL descriptions is increasingly common due to the popularity of top-down design flows exploiting this language. However, the large CPU time required to perform VHDL simulations often represents a major drawback stemming from the adoption of this method. This paper presents some techniques for reducing the time to perform the fault injection experiments. Static and dynamic methods are proposed to analyze the list of faults to be injected, and for removing faults as soon as their behaviour is known. Common features available in most VHDL simulation environments are also exploited. Experimental results show that the proposed techniques are able to reduce the time required by a typical fault injection campaign by a factor ranging from 51% to 96%.","PeriodicalId":334770,"journal":{"name":"Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646)","volume":"178 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124224978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"On-line current testing for a microprocessor based application with an off-chip sensor","authors":"B. Alorda, I. D. Paúl, J. Segura, T. Miller","doi":"10.1109/OLT.2000.856617","DOIUrl":"https://doi.org/10.1109/OLT.2000.856617","url":null,"abstract":"This work presents a prototype architecture that provides on-line IDDQ measurement for a microprocessor-based system. It has been implemented using an IDDQ testable microprocessor (the Intel 386/sup TM/ EX embedded microprocessor) and an off-chip current sensor. Three current test activation modes are supported. A direct test mode through a sensor dedicated pin, a test mode where the microprocessor controls the off-chip sensor, and a P1149.1 driven test. Measurements and architecture operation are detailed.","PeriodicalId":334770,"journal":{"name":"Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646)","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117230451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}