{"title":"On the use of Verilog HDL in the conversion of existing hardware designs to newer technology","authors":"D. Crate","doi":"10.1109/IVC.1996.496016","DOIUrl":"https://doi.org/10.1109/IVC.1996.496016","url":null,"abstract":"The trend towards greater integration of hardware continues, with the attendant benefits of increased density, speed, manufacturability, and reliability. When the updating of an existing design to a new hardware technology becomes necessary, its adaptation must allow for the differences in speed, structure and function of the new hardware medium. With the appearance of hardware description languages and the powerful CAE tools now available, the prospect of automating such a process appears plausible. We consider the \"re-spin\" of a board design from a TTL/PLD implementation to a gate array implementation, and the question of the automated conversion of hardware designs.","PeriodicalId":330849,"journal":{"name":"Proceedings. IEEE International Verilog HDL Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131807870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"LEAH: an introduction to behavioral abstraction and co-simulation using Perl and Verilog","authors":"B. Gelinas, K. Dorman, E. Mednick","doi":"10.1109/IVC.1996.496022","DOIUrl":"https://doi.org/10.1109/IVC.1996.496022","url":null,"abstract":"The paper introduces LEAH, (L2 Emulation Apparatus at a High level), which is a Perl based abstraction of multiprocessor Intel Pentium Pro Processor systems, including processors, memory and I/O subsystems. LEAH is connected to a Verilog simulation through a Unix socket and PLI. Using Perl as its programming base, LEAH abstracts behavior at a high level. Multiple scripts based on the rich facilities of Perl are executed by abstract processors in a multitasking environment. Internal events, such as a cache miss, trigger the use of the Unix socket interface to a Pentium Pro bus interface in the Verilog simulator.","PeriodicalId":330849,"journal":{"name":"Proceedings. IEEE International Verilog HDL Conference","volume":"218 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130420531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Vstyle: a coding style analyzer for synthesizable Verilog","authors":"B. Gelinas","doi":"10.1109/IVC.1996.496018","DOIUrl":"https://doi.org/10.1109/IVC.1996.496018","url":null,"abstract":"The paper describes the implementation of Vstyle, a proprietary Verilog coding style checker implemented in yacc and c. The emphasis is not on any particular set of coding practices, but on how to craft a tool which validates that coding practices are being followed. As with any proprietary tool, the benefits must be weighed with the cost of development and support. The paper demonstrates a method of implementation which delivers the most basic style verification with a modest coding effort, and which can be extended over time to yield increasing benefit.","PeriodicalId":330849,"journal":{"name":"Proceedings. IEEE International Verilog HDL Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134624108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A sockets-based implementation of hardware and software co-design","authors":"A. Herbert","doi":"10.1109/IVC.1996.496021","DOIUrl":"https://doi.org/10.1109/IVC.1996.496021","url":null,"abstract":"The EDA community has provided the tools to automate and accelerate much of the IC design process. However, the development of large ICs still remains expensive and complex. One of the biggest development risks lies in the area of design completeness-that the design will not support all target applications. Design verification tends to be ad hoc, with engineers focusing on verifying the designed functionality with no systematic approach toward verifying all possible applications. This results in partial verification. Design oversights that escape to the IC's prototype stage add time and cost to the project. Clearly, a benefit will result from integration of the end user into the earliest parts of the design cycle. By enabling end users to explore the design space, a more robust design can be yielded.","PeriodicalId":330849,"journal":{"name":"Proceedings. IEEE International Verilog HDL Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134575124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Arnold, A. Wallace, J. Cupal, J. Cowles, F. Engineer
{"title":"Towards a formal model of hardware synthesized from Verilog","authors":"M. Arnold, A. Wallace, J. Cupal, J. Cowles, F. Engineer","doi":"10.1109/IVC.1996.496019","DOIUrl":"https://doi.org/10.1109/IVC.1996.496019","url":null,"abstract":"Formal verification offers a way to prevent costly design errors that are impractical to detect with simulation alone. Successful formal verification of hardware requires using automated theorem provers. Optimal synthesis requires providing high level (behavioral) Verilog to commercial synthesis tools, such as PLDesigner and Synopsys. The paper presents a novel approach, known as the volley technique, that allows a design to be coded in an analogous way both in Verilog HDL and in the LISP like syntax of the Boyer Moore theorem (R.S. Boyer and J.S. Moore, 1988). To illustrate the technique, a simple machine that computes Fibbonaci numbers is designed in Verilog and fabricated as an AMD MACH 210 CPLD.","PeriodicalId":330849,"journal":{"name":"Proceedings. IEEE International Verilog HDL Conference","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125174135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Hierarchical test coverage","authors":"A. Herbert","doi":"10.1109/IVC.1996.496025","DOIUrl":"https://doi.org/10.1109/IVC.1996.496025","url":null,"abstract":"The IOX productivity enhancement required to produce submicron, System On Silicon (SOS) products will come from high level synthesis and design reuse. SOS products will have an infrastructure which preserves the hierarchical structure of the original conceptual thinking. Time to market and quality goals will require the use of previously created and optimized tests for embedded subsystems. Production tests for embedded subsystems will be abstracted from the hierarchical structure of the SOS product. The solution presented describes a method for encapsulating hierarchical information within a test program. A tester architecture to facilitate hierarchical testing is also presented.","PeriodicalId":330849,"journal":{"name":"Proceedings. IEEE International Verilog HDL Conference","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123333867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The Verilog Procedural Interface for the Verilog Hardware Description Language","authors":"C. Dawson, S.K. Pattanam, D. Roberts","doi":"10.1109/IVC.1996.496013","DOIUrl":"https://doi.org/10.1109/IVC.1996.496013","url":null,"abstract":"The Verilog Procedural Interface is a new C programming interface for the Verilog Hardware Description Language. Different Verilog HDL based tools such as simulators, synthesizers, timing analyzers, and parsers could support this interface for applications which extend the tool's functionality. VPI is part of the IEEE 1364 Programming Language Interface standard. VPI is considered to be the third generation procedural interface to Verilog HDL. The first two generations evolved in conjunction with Verilog-XL and the Verilog HDL. This process resulted in interfaces which lacked consistency and functionality for applications. VPI provides a consistent object-oriented access to the complete Verilog HDL language as described in the IEEE 2364 Language Reference Manual. VPI also provides a well defined interface for supporting Verilog-HDL based simulation. It is believed that this interface can be easily extended to meet future needs. A major portion of the VPI functionality is available in the Verilog-XL 2.2 simulator released in 9502. The complete VPI functionality will be available in the Verilog-XL 2.3 simulator to be released in 9504. The paper briefly discusses the evolution of the Verilog HDL programming language interfaces features of the VPI interface, and a set of possible powerful applications.","PeriodicalId":330849,"journal":{"name":"Proceedings. IEEE International Verilog HDL Conference","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128432443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"INCA: a next-generation architecture for simulation","authors":"J. Lawrence, C. Ussery","doi":"10.1109/IVC.1996.496012","DOIUrl":"https://doi.org/10.1109/IVC.1996.496012","url":null,"abstract":"The paper presents INCA, the Interleaved Native-Compiled code Architecture for simulation. INCA is a flexible strategy to create optimized simulations involving multiple design styles, languages, and scheduling paradigms. INCA emphasizes optimized compilers for HDLs vs. more traditional kernel-based approaches. The critical aspects of the architecture include: the separation of kernel and language, usage of elaboration to construct optimal simulation executables, method-based network evaluation, and techniques for mixing different scheduling approaches.","PeriodicalId":330849,"journal":{"name":"Proceedings. IEEE International Verilog HDL Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131390525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Addressing the systems-in-silicon verification challenge: a new approach to logic verification","authors":"S. Caplow, Mike Sottak, D. Kelf","doi":"10.1109/IVC.1996.496024","DOIUrl":"https://doi.org/10.1109/IVC.1996.496024","url":null,"abstract":"The purpose of the paper is to highlight emerging electronic design requirements, and their effect an simulation, and then to describe a new simulation architecture which meets many of the needs discussed. The paper examines the effect of new capabilities offered by silicon vendors on modern IC designs, and then breaks down this effect into design challenges. These challenges are then equated with requirements for HDL simulation. A new simulation architecture is then described which provides the answer to many of the suggested simulation issues.","PeriodicalId":330849,"journal":{"name":"Proceedings. IEEE International Verilog HDL Conference","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132578902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Faster Verilog simulations using a cycle based programming methodology","authors":"M. Becker","doi":"10.1109/IVC.1996.496014","DOIUrl":"https://doi.org/10.1109/IVC.1996.496014","url":null,"abstract":"Verilog is a hardware description language which can be used to verify that hardware functions correctly and within the required timing constraints. If timing is verified using other tools, functional testing speeds can be improved by an order of magnitude or more by using a cycle based simulator. However this restricts users to a sub-set of the verilog grammar. The paper describes the cycle based programming (CBP) methodology whereby hardware designs are implemented in Verilog, but bus functional models (BFM) and test programs are written in a higher level programming language. A programming interface and examples of Verilog language like constructs (forks, joins, waits, etc.) are presented.","PeriodicalId":330849,"journal":{"name":"Proceedings. IEEE International Verilog HDL Conference","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130866574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}