Proceedings. IEEE International Verilog HDL Conference最新文献_第2页

Multi-methodology design: an experimental comparison 多方法设计:实验比较

Proceedings. IEEE International Verilog HDL Conference Pub Date : 1996-03-26 DOI: 10.1109/IVC.1996.496017

R. Prasad, H. Kobayashi

引用次数: 2

An architecture for a verilog hardware accelerator verilog硬件加速器的体系结构

Proceedings. IEEE International Verilog HDL Conference Pub Date : 1996-03-26 DOI: 10.1109/IVC.1996.496011

C. Burns

引用次数: 6

Synthesizing multi-phase HDL programs 合成多相HDL程序

Proceedings. IEEE International Verilog HDL Conference Pub Date : 1996-03-26 DOI: 10.1109/IVC.1996.496020

Szu-Tsung Cheng, R. Brayton

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引用次数: 7

Formal verification-a viable alternative to simulation? 正式验证——模拟的可行替代方案?

Proceedings. IEEE International Verilog HDL Conference Pub Date : 1996-03-26 DOI: 10.1109/IVC.1996.496023

A. Nordstrøm

引用次数: 6

ASIC design validation in a system context 系统环境中的ASIC设计验证

Proceedings. IEEE International Verilog HDL Conference Pub Date : 1996-03-26 DOI: 10.1109/IVC.1996.496026

J. Bartlett

引用次数: 1

VIP: a Verilog Interpreter for Preprocessing 用于预处理的Verilog解释器

Proceedings. IEEE International Verilog HDL Conference Pub Date : 1996-03-26 DOI: 10.1109/IVC.1996.496015

S. Mittra

引用次数: 0