{"title":"verilog硬件加速器的体系结构","authors":"C. Burns","doi":"10.1109/IVC.1996.496011","DOIUrl":null,"url":null,"abstract":"An architecture of a verilog hardware accelerator is presented. In addition to logic simulation using discrete event simulation in hardware, other aspects of the verilog language, including behavioral simulation, module path delays, and timing checks are addressed in the context of a hardware accelerator.","PeriodicalId":330849,"journal":{"name":"Proceedings. IEEE International Verilog HDL Conference","volume":"704 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"An architecture for a verilog hardware accelerator\",\"authors\":\"C. Burns\",\"doi\":\"10.1109/IVC.1996.496011\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An architecture of a verilog hardware accelerator is presented. In addition to logic simulation using discrete event simulation in hardware, other aspects of the verilog language, including behavioral simulation, module path delays, and timing checks are addressed in the context of a hardware accelerator.\",\"PeriodicalId\":330849,\"journal\":{\"name\":\"Proceedings. IEEE International Verilog HDL Conference\",\"volume\":\"704 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-03-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings. IEEE International Verilog HDL Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IVC.1996.496011\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. IEEE International Verilog HDL Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IVC.1996.496011","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An architecture for a verilog hardware accelerator
An architecture of a verilog hardware accelerator is presented. In addition to logic simulation using discrete event simulation in hardware, other aspects of the verilog language, including behavioral simulation, module path delays, and timing checks are addressed in the context of a hardware accelerator.
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