VIP: a Verilog Interpreter for Preprocessing

Abstract

The paper describes VIP, a Verilog Interpreter for Preprocessing. The single pass interpreter converts the extended standard of the Verilog language proposed in LRM2.0a by OVI to the existing standard as in LRM1.0, thus enabling the simulation of the newly written code by the existing simulators. Even if the upcoming standard of the IEEE working committee 1364 disregards the LRM2.0a standard this tool will continue to be an important option for easy code management in future. The two new features which have been included to be checked by the interpreter are the array of instances and the parameterized macro definition. Also the flexibility and performance of the interpreter has been compared with the other existing preprocessor.