Formal verification-a viable alternative to simulation?

Abstract

Functional validation and regression simulations constitute a large part of the entire ASIC design process and schedule. The drive to decrease time to market has resulted in pressure to reduce total simulation times. Formal verification addresses the schedule problem by eliminating the need for regression simulations. The paper investigates whether formal verification is a viable alternative to regression simulations for functional verification in a Verilog based design flow. The investigative methods were based on applying formal verification on all steps in the verification process. It is concluded that regression simulations can be mostly replaced by formal verification.