Vstyle: a coding style analyzer for synthesizable Verilog

Abstract

The paper describes the implementation of Vstyle, a proprietary Verilog coding style checker implemented in yacc and c. The emphasis is not on any particular set of coding practices, but on how to craft a tool which validates that coding practices are being followed. As with any proprietary tool, the benefits must be weighed with the cost of development and support. The paper demonstrates a method of implementation which delivers the most basic style verification with a modest coding effort, and which can be extended over time to yield increasing benefit.