Addressing the systems-in-silicon verification challenge: a new approach to logic verification

Abstract

The purpose of the paper is to highlight emerging electronic design requirements, and their effect an simulation, and then to describe a new simulation architecture which meets many of the needs discussed. The paper examines the effect of new capabilities offered by silicon vendors on modern IC designs, and then breaks down this effect into design challenges. These challenges are then equated with requirements for HDL simulation. A new simulation architecture is then described which provides the answer to many of the suggested simulation issues.