Faster Verilog simulations using a cycle based programming methodology

Abstract

Verilog is a hardware description language which can be used to verify that hardware functions correctly and within the required timing constraints. If timing is verified using other tools, functional testing speeds can be improved by an order of magnitude or more by using a cycle based simulator. However this restricts users to a sub-set of the verilog grammar. The paper describes the cycle based programming (CBP) methodology whereby hardware designs are implemented in Verilog, but bus functional models (BFM) and test programs are written in a higher level programming language. A programming interface and examples of Verilog language like constructs (forks, joins, waits, etc.) are presented.